[U-Boot] [PATCH v2 09/22] arm: dts: Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd]

Peng Fan peng.fan at nxp.com
Tue Jan 29 13:34:41 UTC 2019



> -----Original Message-----
> From: Abel Vesa
> Sent: 2019年1月29日 19:31
> To: Tom Rini <trini at konsulko.com>; Fabio Estevam
> <fabio.estevam at nxp.com>; u-boot at lists.denx.de; dl-uboot-imx
> <uboot-imx at nxp.com>; Peng Fan <peng.fan at nxp.com>
> Cc: Nitin Garg <nitin.garg at nxp.com>; Abel Vesa <abel.vesa at nxp.com>
> Subject: [PATCH v2 09/22] arm: dts: Update all the dts[i] files for
> imx6[q|qp|dl] sabre[auto|sd]
> 
> Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd] to the ones
> from kernel v4.20 (commit 8fe28cb58bcb2).
> 
> Signed-off-by: Abel Vesa <abel.vesa at nxp.com>

Acked-by: Peng Fan <peng.fan at nxp.com>

> ---
>  arch/arm/dts/Makefile               |   8 +-
>  arch/arm/dts/imx6dl-sabreauto.dts   |  13 +
>  arch/arm/dts/imx6dl-sabresd.dts     |  18 +
>  arch/arm/dts/imx6dl.dtsi            | 306 ++++++++++++--
>  arch/arm/dts/imx6q-sabreauto.dts    |  18 +
>  arch/arm/dts/imx6q-sabresd.dts      |  23 +
>  arch/arm/dts/imx6q.dtsi             | 310 ++++++++++++--
>  arch/arm/dts/imx6qdl-sabreauto.dtsi | 810
> ++++++++++++++++++++++++++++++++++++
>  arch/arm/dts/imx6qdl-sabresd.dtsi   | 741
> +++++++++++++++++++++++++++++++++
>  arch/arm/dts/imx6qdl.dtsi           | 455 +++++++++++---------
>  arch/arm/dts/imx6qp-sabreauto.dts   |  55 +++
>  arch/arm/dts/imx6qp-sabresd.dts     |  55 +++
>  arch/arm/dts/imx6qp.dtsi            | 115 +++++
>  13 files changed, 2669 insertions(+), 258 deletions(-)
>  create mode 100644 arch/arm/dts/imx6dl-sabreauto.dts
>  create mode 100644 arch/arm/dts/imx6dl-sabresd.dts
>  create mode 100644 arch/arm/dts/imx6q-sabreauto.dts
>  create mode 100644 arch/arm/dts/imx6q-sabresd.dts
>  create mode 100644 arch/arm/dts/imx6qdl-sabreauto.dtsi
>  create mode 100644 arch/arm/dts/imx6qdl-sabresd.dtsi
>  create mode 100644 arch/arm/dts/imx6qp-sabreauto.dts
>  create mode 100644 arch/arm/dts/imx6qp-sabresd.dts
>  create mode 100644 arch/arm/dts/imx6qp.dtsi
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 5c3225b..c18da3d 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -443,7 +443,13 @@ dtb-$(CONFIG_MX6QDL) += \
>  	imx6q-icore.dtb \
>  	imx6q-icore-mipi.dtb \
>  	imx6q-icore-rqs.dtb \
> -	imx6q-logicpd.dtb
> +	imx6q-logicpd.dtb \
> +	imx6q-sabreauto.dtb \
> +	imx6q-sabresd.dtb \
> +	imx6dl-sabreauto.dtb \
> +	imx6dl-sabresd.dtb \
> +	imx6qp-sabreauto.dtb \
> +	imx6qp-sabresd.dtb
> 
>  dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
> 
> diff --git a/arch/arm/dts/imx6dl-sabreauto.dts
> b/arch/arm/dts/imx6dl-sabreauto.dts
> new file mode 100644
> index 0000000..660d52a
> --- /dev/null
> +++ b/arch/arm/dts/imx6dl-sabreauto.dts
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (C) 2013 Freescale Semiconductor, Inc.
> +
> +/dts-v1/;
> +
> +#include "imx6dl.dtsi"
> +#include "imx6qdl-sabreauto.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
> +	compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
> +};
> diff --git a/arch/arm/dts/imx6dl-sabresd.dts
> b/arch/arm/dts/imx6dl-sabresd.dts
> new file mode 100644
> index 0000000..cd6bbf2
> --- /dev/null
> +++ b/arch/arm/dts/imx6dl-sabresd.dts
> @@ -0,0 +1,18 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (C) 2013 Freescale Semiconductor, Inc.
> +
> +/dts-v1/;
> +
> +#include "imx6dl.dtsi"
> +#include "imx6qdl-sabresd.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
> +	compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
> +};
> +
> +&ipu1_csi1_from_ipu1_csi1_mux {
> +	clock-lanes = <0>;
> +	data-lanes = <1 2>;
> +};
> diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi
> index 9a4c22c..f0607eb 100644
> --- a/arch/arm/dts/imx6dl.dtsi
> +++ b/arch/arm/dts/imx6dl.dtsi
> @@ -1,12 +1,6 @@
> -
> -/*
> - * Copyright 2013 Freescale Semiconductor, Inc.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - *
> - */
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright 2013 Freescale Semiconductor, Inc.
> 
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include "imx6dl-pinfunc.h"
> @@ -39,6 +33,7 @@
>  				396000	1175000
>  			>;
>  			clock-latency = <61036>; /* two CLK32 periods */
> +			#cooling-cells = <2>;
>  			clocks = <&clks IMX6QDL_CLK_ARM>,
>  				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
>  				 <&clks IMX6QDL_CLK_STEP>,
> @@ -56,39 +51,57 @@
>  			device_type = "cpu";
>  			reg = <1>;
>  			next-level-cache = <&L2>;
> +			operating-points = <
> +				/* kHz    uV */
> +				996000  1250000
> +				792000  1175000
> +				396000  1150000
> +			>;
> +			fsl,soc-operating-points = <
> +				/* ARM kHz  SOC-PU uV */
> +				996000	1175000
> +				792000	1175000
> +				396000	1175000
> +			>;
> +			clock-latency = <61036>; /* two CLK32 periods */
> +			clocks = <&clks IMX6QDL_CLK_ARM>,
> +				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
> +				 <&clks IMX6QDL_CLK_STEP>,
> +				 <&clks IMX6QDL_CLK_PLL1_SW>,
> +				 <&clks IMX6QDL_CLK_PLL1_SYS>;
> +			clock-names = "arm", "pll2_pfd2_396m", "step",
> +				      "pll1_sw", "pll1_sys";
> +			arm-supply = <&reg_arm>;
> +			pu-supply = <&reg_pu>;
> +			soc-supply = <&reg_soc>;
>  		};
>  	};
> 
>  	soc {
> -		ocram: sram at 00900000 {
> +		ocram: sram at 900000 {
>  			compatible = "mmio-sram";
>  			reg = <0x00900000 0x20000>;
>  			clocks = <&clks IMX6QDL_CLK_OCRAM>;
>  		};
> 
> -		aips1: aips-bus at 02000000 {
> -			iomuxc: iomuxc at 020e0000 {
> +		aips1: aips-bus at 2000000 {
> +			iomuxc: iomuxc at 20e0000 {
>  				compatible = "fsl,imx6dl-iomuxc";
>  			};
> 
> -			pxp: pxp at 020f0000 {
> +			pxp: pxp at 20f0000 {
>  				reg = <0x020f0000 0x4000>;
>  				interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
>  			};
> 
> -			epdc: epdc at 020f4000 {
> +			epdc: epdc at 20f4000 {
>  				reg = <0x020f4000 0x4000>;
>  				interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
>  			};
> -
> -			lcdif: lcdif at 020f8000 {
> -				reg = <0x020f8000 0x4000>;
> -				interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
> -			};
>  		};
> 
> -		aips2: aips-bus at 02100000 {
> -			i2c4: i2c at 021f8000 {
> +		aips2: aips-bus at 2100000 {
> +			i2c4: i2c at 21f8000 {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
>  				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
> @@ -100,14 +113,177 @@
>  		};
>  	};
> 
> +	capture-subsystem {
> +		compatible = "fsl,imx-capture-subsystem";
> +		ports = <&ipu1_csi0>, <&ipu1_csi1>;
> +	};
> +
>  	display-subsystem {
>  		compatible = "fsl,imx-display-subsystem";
>  		ports = <&ipu1_di0>, <&ipu1_di1>;
>  	};
> +};
> +
> +&gpio1 {
> +	gpio-ranges = <&iomuxc  0 131 2>, <&iomuxc  2 137 8>, <&iomuxc 10
> 189 2>,
> +		      <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192
> 1>,
> +		      <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184
> 1>,
> +		      <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188
> 1>,
> +		      <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127
> 1>,
> +		      <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130
> 1>,
> +		      <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
> +};
> +
> +&gpio2 {
> +	gpio-ranges = <&iomuxc  0 161 8>, <&iomuxc  8 208 8>, <&iomuxc 16
> 74 1>,
> +		      <&iomuxc 17  73 1>, <&iomuxc 18  72 1>, <&iomuxc 19
> 71 1>,
> +		      <&iomuxc 20  70 1>, <&iomuxc 21  69 1>, <&iomuxc 22
> 68 1>,
> +		      <&iomuxc 23  79 2>, <&iomuxc 25 118 2>, <&iomuxc 27
> 117 1>,
> +		      <&iomuxc 28 113 4>;
> +};
> +
> +&gpio3 {
> +	gpio-ranges = <&iomuxc  0 97  2>, <&iomuxc 2 105 8>, <&iomuxc 10
> 99 6>,
> +		      <&iomuxc 16 81 16>;
> +};
> +
> +&gpio4 {
> +	gpio-ranges = <&iomuxc  5 136 1>, <&iomuxc  6 145 1>, <&iomuxc  7
> 150 1>,
> +		      <&iomuxc  8 146 1>, <&iomuxc  9 151 1>, <&iomuxc 10
> 147 1>,
> +		      <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153
> 1>,
> +		      <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16
> 39 7>,
> +		      <&iomuxc 23  56 1>, <&iomuxc 24  61 7>, <&iomuxc 31
> 46 1>;
> +};
> 
> -	gpu-subsystem {
> -		compatible = "fsl,imx-gpu-subsystem";
> -		cores = <&gpu_2d>, <&gpu_3d>;
> +&gpio5 {
> +	gpio-ranges = <&iomuxc  0 120 1>, <&iomuxc  2 77 1>, <&iomuxc  4
> 76 1>,
> +		      <&iomuxc  5  47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37
> 1>,
> +		      <&iomuxc 19  36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38
> 1>,
> +		      <&iomuxc 22  29 6>, <&iomuxc 28 19 4>;
> +};
> +
> +&gpio6 {
> +	gpio-ranges = <&iomuxc  0  23 6>, <&iomuxc  6  75 1>, <&iomuxc
> 7 156 1>,
> +		      <&iomuxc  8 155 1>, <&iomuxc  9 170 1>, <&iomuxc 10
> 169 1>,
> +		      <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204
> 1>,
> +		      <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177
> 4>,
> +		      <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181
> 1>,
> +		      <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31
> 78 1>;
> +};
> +
> +&gpio7 {
> +	gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc  1 201 1>, <&iomuxc  2
> 196 1>,
> +		      <&iomuxc 3 195 1>, <&iomuxc  4 197 4>, <&iomuxc  8 205
> 1>,
> +		      <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133
> 3>;
> +};
> +
> +&gpr {
> +	ipu1_csi0_mux {
> +		compatible = "video-mux";
> +		mux-controls = <&mux 0>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port at 0 {
> +			reg = <0>;
> +
> +			ipu1_csi0_mux_from_mipi_vc0: endpoint {
> +				remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
> +			};
> +		};
> +
> +		port at 1 {
> +			reg = <1>;
> +
> +			ipu1_csi0_mux_from_mipi_vc1: endpoint {
> +				remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
> +			};
> +		};
> +
> +		port at 2 {
> +			reg = <2>;
> +
> +			ipu1_csi0_mux_from_mipi_vc2: endpoint {
> +				remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
> +			};
> +		};
> +
> +		port at 3 {
> +			reg = <3>;
> +
> +			ipu1_csi0_mux_from_mipi_vc3: endpoint {
> +				remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
> +			};
> +		};
> +
> +		port at 4 {
> +			reg = <4>;
> +
> +			ipu1_csi0_mux_from_parallel_sensor: endpoint {
> +			};
> +		};
> +
> +		port at 5 {
> +			reg = <5>;
> +
> +			ipu1_csi0_mux_to_ipu1_csi0: endpoint {
> +				remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
> +			};
> +		};
> +	};
> +
> +	ipu1_csi1_mux {
> +		compatible = "video-mux";
> +		mux-controls = <&mux 1>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port at 0 {
> +			reg = <0>;
> +
> +			ipu1_csi1_mux_from_mipi_vc0: endpoint {
> +				remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
> +			};
> +		};
> +
> +		port at 1 {
> +			reg = <1>;
> +
> +			ipu1_csi1_mux_from_mipi_vc1: endpoint {
> +				remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
> +			};
> +		};
> +
> +		port at 2 {
> +			reg = <2>;
> +
> +			ipu1_csi1_mux_from_mipi_vc2: endpoint {
> +				remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
> +			};
> +		};
> +
> +		port at 3 {
> +			reg = <3>;
> +
> +			ipu1_csi1_mux_from_mipi_vc3: endpoint {
> +				remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
> +			};
> +		};
> +
> +		port at 4 {
> +			reg = <4>;
> +
> +			ipu1_csi1_mux_from_parallel_sensor: endpoint {
> +			};
> +		};
> +
> +		port at 5 {
> +			reg = <5>;
> +
> +			ipu1_csi1_mux_to_ipu1_csi1: endpoint {
> +				remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
> +			};
> +		};
>  	};
>  };
> 
> @@ -119,6 +295,12 @@
>  	compatible = "fsl,imx6dl-hdmi";
>  };
> 
> +&ipu1_csi1 {
> +	ipu1_csi1_from_ipu1_csi1_mux: endpoint {
> +		remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
> +	};
> +};
> +
>  &ldb {
>  	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks
> IMX6QDL_CLK_LDB_DI1_SEL>,
>  		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks
> IMX6QDL_CLK_IPU1_DI1_SEL>,
> @@ -128,6 +310,82 @@
>  		      "di0", "di1";
>  };
> 
> +&mipi_csi {
> +	port at 1 {
> +		reg = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		mipi_vc0_to_ipu1_csi0_mux: endpoint at 0 {
> +			reg = <0>;
> +			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
> +		};
> +
> +		mipi_vc0_to_ipu1_csi1_mux: endpoint at 1 {
> +			reg = <1>;
> +			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
> +		};
> +	};
> +
> +	port at 2 {
> +		reg = <2>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		mipi_vc1_to_ipu1_csi0_mux: endpoint at 0 {
> +			reg = <0>;
> +			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
> +		};
> +
> +		mipi_vc1_to_ipu1_csi1_mux: endpoint at 1 {
> +			reg = <1>;
> +			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
> +		};
> +	};
> +
> +	port at 3 {
> +		reg = <3>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		mipi_vc2_to_ipu1_csi0_mux: endpoint at 0 {
> +			reg = <0>;
> +			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
> +		};
> +
> +		mipi_vc2_to_ipu1_csi1_mux: endpoint at 1 {
> +			reg = <1>;
> +			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
> +		};
> +	};
> +
> +	port at 4 {
> +		reg = <4>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		mipi_vc3_to_ipu1_csi0_mux: endpoint at 0 {
> +			reg = <0>;
> +			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
> +		};
> +
> +		mipi_vc3_to_ipu1_csi1_mux: endpoint at 1 {
> +			reg = <1>;
> +			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
> +		};
> +	};
> +};
> +
> +&mux {
> +	mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
> +			<0x34 0x00000038>, /* IPU_CSI1_MUX */
> +			<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
> +			<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
> +			<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
> +			<0x28 0x00000003>, /* DCIC1_MUX_CTL */
> +			<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
> +};
> +
>  &vpu {
>  	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
>  };
> diff --git a/arch/arm/dts/imx6q-sabreauto.dts
> b/arch/arm/dts/imx6q-sabreauto.dts
> new file mode 100644
> index 0000000..6e981a3
> --- /dev/null
> +++ b/arch/arm/dts/imx6q-sabreauto.dts
> @@ -0,0 +1,18 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +//
> +// Copyright 2012 Freescale Semiconductor, Inc.
> +// Copyright 2011 Linaro Ltd.
> +
> +/dts-v1/;
> +
> +#include "imx6q.dtsi"
> +#include "imx6qdl-sabreauto.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX6 Quad SABRE Automotive Board";
> +	compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
> +};
> +
> +&sata {
> +	status = "okay";
> +};
> diff --git a/arch/arm/dts/imx6q-sabresd.dts
> b/arch/arm/dts/imx6q-sabresd.dts
> new file mode 100644
> index 0000000..eec9446
> --- /dev/null
> +++ b/arch/arm/dts/imx6q-sabresd.dts
> @@ -0,0 +1,23 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +//
> +// Copyright 2012 Freescale Semiconductor, Inc.
> +// Copyright 2011 Linaro Ltd.
> +
> +/dts-v1/;
> +
> +#include "imx6q.dtsi"
> +#include "imx6qdl-sabresd.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX6 Quad SABRE Smart Device Board";
> +	compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
> +};
> +
> +&sata {
> +	status = "okay";
> +};
> +
> +&ipu1_csi1_from_mipi_vc1 {
> +	clock-lanes = <0>;
> +	data-lanes = <1 2>;
> +};
> diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
> index c30c836..8381d24 100644
> --- a/arch/arm/dts/imx6q.dtsi
> +++ b/arch/arm/dts/imx6q.dtsi
> @@ -1,12 +1,6 @@
> -
> -/*
> - * Copyright 2013 Freescale Semiconductor, Inc.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - *
> - */
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright 2013 Freescale Semiconductor, Inc.
> 
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include "imx6q-pinfunc.h"
> @@ -44,6 +38,7 @@
>  				396000	1175000
>  			>;
>  			clock-latency = <61036>; /* two CLK32 periods */
> +			#cooling-cells = <2>;
>  			clocks = <&clks IMX6QDL_CLK_ARM>,
>  				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
>  				 <&clks IMX6QDL_CLK_STEP>,
> @@ -56,38 +51,119 @@
>  			soc-supply = <&reg_soc>;
>  		};
> 
> -		cpu at 1 {
> +		cpu1: cpu at 1 {
>  			compatible = "arm,cortex-a9";
>  			device_type = "cpu";
>  			reg = <1>;
>  			next-level-cache = <&L2>;
> +			operating-points = <
> +				/* kHz    uV */
> +				1200000 1275000
> +				996000  1250000
> +				852000  1250000
> +				792000  1175000
> +				396000  975000
> +			>;
> +			fsl,soc-operating-points = <
> +				/* ARM kHz  SOC-PU uV */
> +				1200000 1275000
> +				996000	1250000
> +				852000	1250000
> +				792000	1175000
> +				396000	1175000
> +			>;
> +			clock-latency = <61036>; /* two CLK32 periods */
> +			clocks = <&clks IMX6QDL_CLK_ARM>,
> +				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
> +				 <&clks IMX6QDL_CLK_STEP>,
> +				 <&clks IMX6QDL_CLK_PLL1_SW>,
> +				 <&clks IMX6QDL_CLK_PLL1_SYS>;
> +			clock-names = "arm", "pll2_pfd2_396m", "step",
> +				      "pll1_sw", "pll1_sys";
> +			arm-supply = <&reg_arm>;
> +			pu-supply = <&reg_pu>;
> +			soc-supply = <&reg_soc>;
>  		};
> 
> -		cpu at 2 {
> +		cpu2: cpu at 2 {
>  			compatible = "arm,cortex-a9";
>  			device_type = "cpu";
>  			reg = <2>;
>  			next-level-cache = <&L2>;
> +			operating-points = <
> +				/* kHz    uV */
> +				1200000 1275000
> +				996000  1250000
> +				852000  1250000
> +				792000  1175000
> +				396000  975000
> +			>;
> +			fsl,soc-operating-points = <
> +				/* ARM kHz  SOC-PU uV */
> +				1200000 1275000
> +				996000	1250000
> +				852000	1250000
> +				792000	1175000
> +				396000	1175000
> +			>;
> +			clock-latency = <61036>; /* two CLK32 periods */
> +			clocks = <&clks IMX6QDL_CLK_ARM>,
> +				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
> +				 <&clks IMX6QDL_CLK_STEP>,
> +				 <&clks IMX6QDL_CLK_PLL1_SW>,
> +				 <&clks IMX6QDL_CLK_PLL1_SYS>;
> +			clock-names = "arm", "pll2_pfd2_396m", "step",
> +				      "pll1_sw", "pll1_sys";
> +			arm-supply = <&reg_arm>;
> +			pu-supply = <&reg_pu>;
> +			soc-supply = <&reg_soc>;
>  		};
> 
> -		cpu at 3 {
> +		cpu3: cpu at 3 {
>  			compatible = "arm,cortex-a9";
>  			device_type = "cpu";
>  			reg = <3>;
>  			next-level-cache = <&L2>;
> +			operating-points = <
> +				/* kHz    uV */
> +				1200000 1275000
> +				996000  1250000
> +				852000  1250000
> +				792000  1175000
> +				396000  975000
> +			>;
> +			fsl,soc-operating-points = <
> +				/* ARM kHz  SOC-PU uV */
> +				1200000 1275000
> +				996000	1250000
> +				852000	1250000
> +				792000	1175000
> +				396000	1175000
> +			>;
> +			clock-latency = <61036>; /* two CLK32 periods */
> +			clocks = <&clks IMX6QDL_CLK_ARM>,
> +				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
> +				 <&clks IMX6QDL_CLK_STEP>,
> +				 <&clks IMX6QDL_CLK_PLL1_SW>,
> +				 <&clks IMX6QDL_CLK_PLL1_SYS>;
> +			clock-names = "arm", "pll2_pfd2_396m", "step",
> +				      "pll1_sw", "pll1_sys";
> +			arm-supply = <&reg_arm>;
> +			pu-supply = <&reg_pu>;
> +			soc-supply = <&reg_soc>;
>  		};
>  	};
> 
>  	soc {
> -		ocram: sram at 00900000 {
> +		ocram: sram at 900000 {
>  			compatible = "mmio-sram";
>  			reg = <0x00900000 0x40000>;
>  			clocks = <&clks IMX6QDL_CLK_OCRAM>;
>  		};
> 
> -		aips-bus at 02000000 { /* AIPS1 */
> -			spba-bus at 02000000 {
> -				ecspi5: ecspi at 02018000 {
> +		aips-bus at 2000000 { /* AIPS1 */
> +			spba-bus at 2000000 {
> +				ecspi5: spi at 2018000 {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
>  					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
> @@ -96,18 +172,18 @@
>  					clocks = <&clks IMX6Q_CLK_ECSPI5>,
>  						 <&clks IMX6Q_CLK_ECSPI5>;
>  					clock-names = "ipg", "per";
> -					dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
> +					dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
>  					dma-names = "rx", "tx";
>  					status = "disabled";
>  				};
>  			};
> 
> -			iomuxc: iomuxc at 020e0000 {
> +			iomuxc: iomuxc at 20e0000 {
>  				compatible = "fsl,imx6q-iomuxc";
>  			};
>  		};
> 
> -		sata: sata at 02200000 {
> +		sata: sata at 2200000 {
>  			compatible = "fsl,imx6q-ahci";
>  			reg = <0x02200000 0x4000>;
>  			interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
> @@ -118,17 +194,17 @@
>  			status = "disabled";
>  		};
> 
> -		gpu_vg: gpu at 02204000 {
> +		gpu_vg: gpu at 2204000 {
>  			compatible = "vivante,gc";
>  			reg = <0x02204000 0x4000>;
>  			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
>  				 <&clks IMX6QDL_CLK_GPU2D_CORE>;
>  			clock-names = "bus", "core";
> -			power-domains = <&gpc 1>;
> +			power-domains = <&pd_pu>;
>  		};
> 
> -		ipu2: ipu at 02800000 {
> +		ipu2: ipu at 2800000 {
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			compatible = "fsl,imx6q-ipu";
> @@ -143,10 +219,18 @@
> 
>  			ipu2_csi0: port at 0 {
>  				reg = <0>;
> +
> +				ipu2_csi0_from_mipi_vc2: endpoint {
> +					remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
> +				};
>  			};
> 
>  			ipu2_csi1: port at 1 {
>  				reg = <1>;
> +
> +				ipu2_csi1_from_ipu2_csi1_mux: endpoint {
> +					remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
> +				};
>  			};
> 
>  			ipu2_di0: port at 2 {
> @@ -154,22 +238,27 @@
>  				#size-cells = <0>;
>  				reg = <2>;
> 
> -				ipu2_di0_disp0: disp0-endpoint {
> +				ipu2_di0_disp0: endpoint at 0 {
> +					reg = <0>;
>  				};
> 
> -				ipu2_di0_hdmi: hdmi-endpoint {
> +				ipu2_di0_hdmi: endpoint at 1 {
> +					reg = <1>;
>  					remote-endpoint = <&hdmi_mux_2>;
>  				};
> 
> -				ipu2_di0_mipi: mipi-endpoint {
> +				ipu2_di0_mipi: endpoint at 2 {
> +					reg = <2>;
>  					remote-endpoint = <&mipi_mux_2>;
>  				};
> 
> -				ipu2_di0_lvds0: lvds0-endpoint {
> +				ipu2_di0_lvds0: endpoint at 3 {
> +					reg = <3>;
>  					remote-endpoint = <&lvds0_mux_2>;
>  				};
> 
> -				ipu2_di0_lvds1: lvds1-endpoint {
> +				ipu2_di0_lvds1: endpoint at 4 {
> +					reg = <4>;
>  					remote-endpoint = <&lvds1_mux_2>;
>  				};
>  			};
> @@ -179,33 +268,136 @@
>  				#size-cells = <0>;
>  				reg = <3>;
> 
> -				ipu2_di1_hdmi: hdmi-endpoint {
> +				ipu2_di1_hdmi: endpoint at 1 {
> +					reg = <1>;
>  					remote-endpoint = <&hdmi_mux_3>;
>  				};
> 
> -				ipu2_di1_mipi: mipi-endpoint {
> +				ipu2_di1_mipi: endpoint at 2 {
> +					reg = <2>;
>  					remote-endpoint = <&mipi_mux_3>;
>  				};
> 
> -				ipu2_di1_lvds0: lvds0-endpoint {
> +				ipu2_di1_lvds0: endpoint at 3 {
> +					reg = <3>;
>  					remote-endpoint = <&lvds0_mux_3>;
>  				};
> 
> -				ipu2_di1_lvds1: lvds1-endpoint {
> +				ipu2_di1_lvds1: endpoint at 4 {
> +					reg = <4>;
>  					remote-endpoint = <&lvds1_mux_3>;
>  				};
>  			};
>  		};
>  	};
> 
> +	capture-subsystem {
> +		compatible = "fsl,imx-capture-subsystem";
> +		ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
> +	};
> +
>  	display-subsystem {
>  		compatible = "fsl,imx-display-subsystem";
>  		ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
>  	};
> +};
> +
> +&gpio1 {
> +	gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc
> 3 139 1>,
> +		      <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7
> 144 2>,
> +		      <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13
> 20 1>,
> +		      <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16
> 208 1>,
> +		      <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21
> 209 1>,
> +		      <&iomuxc 22 116 10>;
> +};
> +
> +&gpio2 {
> +	gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30
> 35 1>,
> +		      <&iomuxc 31  44  1>;
> +};
> +
> +&gpio3 {
> +	gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45
> 8>;
> +};
> +
> +&gpio4 {
> +	gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87
> 16>;
> +};
> +
> +&gpio5 {
> +	gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc
> 4 53 1>,
> +		      <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
> +};
> +
> +&gpio6 {
> +	gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7
> 181  5>,
> +		      <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19
> 22 12>,
> +		      <&iomuxc 31  86 1>;
> +};
> +
> +&gpio7 {
> +	gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146
> 3>;
> +};
> +
> +&gpr {
> +	ipu1_csi0_mux {
> +		compatible = "video-mux";
> +		mux-controls = <&mux 0>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port at 0 {
> +			reg = <0>;
> +
> +			ipu1_csi0_mux_from_mipi_vc0: endpoint {
> +				remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
> +			};
> +		};
> +
> +		port at 1 {
> +			reg = <1>;
> +
> +			ipu1_csi0_mux_from_parallel_sensor: endpoint {
> +			};
> +		};
> 
> -	gpu-subsystem {
> -		compatible = "fsl,imx-gpu-subsystem";
> -		cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
> +		port at 2 {
> +			reg = <2>;
> +
> +			ipu1_csi0_mux_to_ipu1_csi0: endpoint {
> +				remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
> +			};
> +		};
> +	};
> +
> +	ipu2_csi1_mux {
> +		compatible = "video-mux";
> +		mux-controls = <&mux 1>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port at 0 {
> +			reg = <0>;
> +
> +			ipu2_csi1_mux_from_mipi_vc3: endpoint {
> +				remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
> +			};
> +		};
> +
> +		port at 1 {
> +			reg = <1>;
> +
> +			ipu2_csi1_mux_from_parallel_sensor: endpoint {
> +			};
> +		};
> +
> +		port at 2 {
> +			reg = <2>;
> +
> +			ipu2_csi1_mux_to_ipu2_csi1: endpoint {
> +				remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
> +			};
> +		};
>  	};
>  };
> 
> @@ -229,6 +421,12 @@
>  	};
>  };
> 
> +&ipu1_csi1 {
> +	ipu1_csi1_from_mipi_vc1: endpoint {
> +		remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
> +	};
> +};
> +
>  &ldb {
>  	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks
> IMX6QDL_CLK_LDB_DI1_SEL>,
>  		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks
> IMX6QDL_CLK_IPU1_DI1_SEL>,
> @@ -275,6 +473,40 @@
>  	};
>  };
> 
> +&mipi_csi {
> +	port at 1 {
> +		reg = <1>;
> +
> +		mipi_vc0_to_ipu1_csi0_mux: endpoint {
> +			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
> +		};
> +	};
> +
> +	port at 2 {
> +		reg = <2>;
> +
> +		mipi_vc1_to_ipu1_csi1: endpoint {
> +			remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
> +		};
> +	};
> +
> +	port at 3 {
> +		reg = <3>;
> +
> +		mipi_vc2_to_ipu2_csi0: endpoint {
> +			remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
> +		};
> +	};
> +
> +	port at 4 {
> +		reg = <4>;
> +
> +		mipi_vc3_to_ipu2_csi1_mux: endpoint {
> +			remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
> +		};
> +	};
> +};
> +
>  &mipi_dsi {
>  	ports {
>  		port at 2 {
> @@ -295,6 +527,16 @@
>  	};
>  };
> 
> +&mux {
> +	mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
> +			<0x04 0x00100000>, /* MIPI_IPU2_MUX */
> +			<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
> +			<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
> +			<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
> +			<0x28 0x00000003>, /* DCIC1_MUX_CTL */
> +			<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
> +};
> +
>  &vpu {
>  	compatible = "fsl,imx6q-vpu", "cnm,coda960";
>  };
> diff --git a/arch/arm/dts/imx6qdl-sabreauto.dtsi
> b/arch/arm/dts/imx6qdl-sabreauto.dtsi
> new file mode 100644
> index 0000000..a6dc5c4
> --- /dev/null
> +++ b/arch/arm/dts/imx6qdl-sabreauto.dtsi
> @@ -0,0 +1,810 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +//
> +// Copyright 2012 Freescale Semiconductor, Inc.
> +// Copyright 2011 Linaro Ltd.
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> +	chosen {
> +		stdout-path = &uart4;
> +	};
> +
> +	memory at 10000000 {
> +		reg = <0x10000000 0x80000000>;
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_gpio_leds>;
> +
> +		user {
> +			label = "debug";
> +			gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
> +		};
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_gpio_keys>;
> +
> +		home {
> +			label = "Home";
> +			gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_HOME>;
> +			wakeup-source;
> +		};
> +
> +		back {
> +			label = "Back";
> +			gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_BACK>;
> +			wakeup-source;
> +		};
> +
> +		program {
> +			label = "Program";
> +			gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_PROGRAM>;
> +			wakeup-source;
> +		};
> +
> +		volume-up {
> +			label = "Volume Up";
> +			gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_VOLUMEUP>;
> +			wakeup-source;
> +		};
> +
> +		volume-down {
> +			label = "Volume Down";
> +			gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_VOLUMEDOWN>;
> +			wakeup-source;
> +		};
> +	};
> +
> +	clocks {
> +		codec_osc: anaclk2 {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <24576000>;
> +		};
> +	};
> +
> +	regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		reg_audio: regulator at 0 {
> +			compatible = "regulator-fixed";
> +			reg = <0>;
> +			regulator-name = "cs42888_supply";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			regulator-always-on;
> +		};
> +
> +		reg_usb_h1_vbus: regulator at 1 {
> +			compatible = "regulator-fixed";
> +			reg = <1>;
> +			regulator-name = "usb_h1_vbus";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +		};
> +
> +		reg_usb_otg_vbus: regulator at 2 {
> +			compatible = "regulator-fixed";
> +			reg = <2>;
> +			regulator-name = "usb_otg_vbus";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
> +			enable-active-high;
> +		};
> +	};
> +
> +	sound-cs42888 {
> +		compatible = "fsl,imx6-sabreauto-cs42888",
> +			"fsl,imx-audio-cs42888";
> +		model = "imx-cs42888";
> +		audio-cpu = <&esai>;
> +		audio-asrc = <&asrc>;
> +		audio-codec = <&codec>;
> +		audio-routing =
> +			"Line Out Jack", "AOUT1L",
> +			"Line Out Jack", "AOUT1R",
> +			"Line Out Jack", "AOUT2L",
> +			"Line Out Jack", "AOUT2R",
> +			"Line Out Jack", "AOUT3L",
> +			"Line Out Jack", "AOUT3R",
> +			"Line Out Jack", "AOUT4L",
> +			"Line Out Jack", "AOUT4R",
> +			"AIN1L", "Line In Jack",
> +			"AIN1R", "Line In Jack",
> +			"AIN2L", "Line In Jack",
> +			"AIN2R", "Line In Jack";
> +	};
> +
> +	sound-spdif {
> +		compatible = "fsl,imx-audio-spdif",
> +			   "fsl,imx-sabreauto-spdif";
> +		model = "imx-spdif";
> +		spdif-controller = <&spdif>;
> +		spdif-in;
> +	};
> +
> +	backlight {
> +		compatible = "pwm-backlight";
> +		pwms = <&pwm3 0 5000000>;
> +		brightness-levels = <0 4 8 16 32 64 128 255>;
> +		default-brightness-level = <7>;
> +		status = "okay";
> +	};
> +
> +	i2cmux {
> +		compatible = "i2c-mux-gpio";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_i2c3mux>;
> +		mux-gpios = <&gpio5 4 0>;
> +		i2c-parent = <&i2c3>;
> +		idle-state = <0>;
> +
> +		i2c at 1 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <1>;
> +
> +			adv7180: camera at 21 {
> +				compatible = "adi,adv7180";
> +				reg = <0x21>;
> +				powerdown-gpios = <&max7310_b 2
> GPIO_ACTIVE_LOW>;
> +				interrupt-parent = <&gpio1>;
> +				interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
> +
> +				port {
> +					adv7180_to_ipu1_csi0_mux: endpoint {
> +						remote-endpoint =
> <&ipu1_csi0_mux_from_parallel_sensor>;
> +						bus-width = <8>;
> +					};
> +				};
> +			};
> +
> +			max7310_a: gpio at 30 {
> +				compatible = "maxim,max7310";
> +				reg = <0x30>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +			};
> +
> +			max7310_b: gpio at 32 {
> +				compatible = "maxim,max7310";
> +				reg = <0x32>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_max7310>;
> +				reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
> +			};
> +
> +			max7310_c: gpio at 34 {
> +				compatible = "maxim,max7310";
> +				reg = <0x34>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +			};
> +
> +			light-sensor at 44 {
> +				compatible = "isil,isl29023";
> +				reg = <0x44>;
> +				interrupt-parent = <&gpio5>;
> +				interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
> +			};
> +
> +			magnetometer at e {
> +				compatible = "fsl,mag3110";
> +				reg = <0x0e>;
> +				interrupt-parent = <&gpio2>;
> +				interrupts = <29 IRQ_TYPE_EDGE_RISING>;
> +			};
> +
> +			accelerometer at 1c {
> +				compatible = "fsl,mma8451";
> +				reg = <0x1c>;
> +				interrupt-parent = <&gpio6>;
> +				interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
> +			};
> +		};
> +	};
> +};
> +
> +&ipu1_csi0_from_ipu1_csi0_mux {
> +	bus-width = <8>;
> +};
> +
> +&ipu1_csi0_mux_from_parallel_sensor {
> +	remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
> +	bus-width = <8>;
> +};
> +
> +&ipu1_csi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ipu1_csi0>;
> +};
> +
> +&clks {
> +	assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
> +			  <&clks IMX6QDL_PLL4_BYPASS>,
> +			  <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
> +			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
> +			  <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
> +	assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
> +				 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
> +				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
> +				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
> +	assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
> +};
> +
> +&ecspi1 {
> +	cs-gpios = <&gpio3 19 0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
> +	status = "disabled"; /* pin conflict with WEIM NOR */
> +
> +	flash: m25p80 at 0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "st,m25p32", "jedec,spi-nor";
> +		spi-max-frequency = <20000000>;
> +		reg = <0>;
> +	};
> +};
> +
> +&esai {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_esai>;
> +	assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
> +			  <&clks IMX6QDL_CLK_ESAI_EXTAL>;
> +	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
> +	assigned-clock-rates = <0>, <24576000>;
> +	status = "okay";
> +};
> +
> +&fec {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_enet>;
> +	phy-mode = "rgmii";
> +	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
> +			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
> +	fsl,err006687-workaround-present;
> +	status = "okay";
> +};
> +
> +&gpmi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_gpmi_nand>;
> +	status = "okay";
> +};
> +
> +&hdmi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hdmi_cec>;
> +	ddc-i2c-bus = <&i2c2>;
> +	status = "okay";
> +};
> +
> +&i2c2 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c2>;
> +	status = "okay";
> +
> +	pmic: pfuze100 at 8 {
> +		compatible = "fsl,pfuze100";
> +		reg = <0x08>;
> +
> +		regulators {
> +			sw1a_reg: sw1ab {
> +				regulator-min-microvolt = <300000>;
> +				regulator-max-microvolt = <1875000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <6250>;
> +			};
> +
> +			sw1c_reg: sw1c {
> +				regulator-min-microvolt = <300000>;
> +				regulator-max-microvolt = <1875000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <6250>;
> +			};
> +
> +			sw2_reg: sw2 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			sw3a_reg: sw3a {
> +				regulator-min-microvolt = <400000>;
> +				regulator-max-microvolt = <1975000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			sw3b_reg: sw3b {
> +				regulator-min-microvolt = <400000>;
> +				regulator-max-microvolt = <1975000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			sw4_reg: sw4 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +			};
> +
> +			swbst_reg: swbst {
> +				regulator-min-microvolt = <5000000>;
> +				regulator-max-microvolt = <5150000>;
> +			};
> +
> +			snvs_reg: vsnvs {
> +				regulator-min-microvolt = <1000000>;
> +				regulator-max-microvolt = <3000000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			vref_reg: vrefddr {
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			vgen1_reg: vgen1 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <1550000>;
> +			};
> +
> +			vgen2_reg: vgen2 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <1550000>;
> +			};
> +
> +			vgen3_reg: vgen3 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +			};
> +
> +			vgen4_reg: vgen4 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-always-on;
> +			};
> +
> +			vgen5_reg: vgen5 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-always-on;
> +			};
> +
> +			vgen6_reg: vgen6 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-always-on;
> +			};
> +		};
> +	};
> +
> +	codec: cs42888 at 48 {
> +		compatible = "cirrus,cs42888";
> +		reg = <0x48>;
> +		clocks = <&codec_osc>;
> +		clock-names = "mclk";
> +		VA-supply = <&reg_audio>;
> +		VD-supply = <&reg_audio>;
> +		VLS-supply = <&reg_audio>;
> +		VLC-supply = <&reg_audio>;
> +	};
> +
> +	touchscreen at 4 {
> +		compatible = "eeti,egalax_ts";
> +		reg = <0x04>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_egalax_int>;
> +		interrupt-parent = <&gpio2>;
> +		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
> +		wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
> +	};
> +};
> +
> +&i2c3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c3>;
> +	status = "okay";
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hog>;
> +
> +	imx6qdl-sabreauto {
> +		pinctrl_hog: hoggrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
> +				MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
> +				MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
> +			>;
> +		};
> +
> +		pinctrl_ecspi1: ecspi1grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
> +				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
> +				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
> +			>;
> +		};
> +
> +		pinctrl_ecspi1_cs: ecspi1cs {
> +			fsl,pins = <
> +				MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
> +			>;
> +		};
> +
> +		pinctrl_egalax_int: egalax-intgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_EIM_EB0__GPIO2_IO28		0xb0b1
> +			>;
> +		};
> +
> +		pinctrl_enet: enetgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_KEY_COL1__ENET_MDIO		0x1b0b0
> +				MX6QDL_PAD_KEY_COL2__ENET_MDC		0x1b0b0
> +				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
> +				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
> +				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
> +				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
> +				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
> +				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
> +				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
> +				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
> +				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
> +				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
> +				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
> +				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
> +				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL
> 	0x1b030
> +				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
> +			>;
> +		};
> +
> +		pinctrl_esai: esaigrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
> +				MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS    0x1b030
> +				MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
> +				MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3     0x1b030
> +				MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1  0x1b030
> +				MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0   0x1b030
> +				MX6QDL_PAD_GPIO_17__ESAI_TX0        0x1b030
> +				MX6QDL_PAD_NANDF_CS3__ESAI_TX1      0x1b030
> +				MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK   0x1b030
> +				MX6QDL_PAD_GPIO_9__ESAI_RX_FS       0x1b030
> +			>;
> +		};
> +
> +		pinctrl_gpio_keys: gpiokeysgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD2_CMD__GPIO1_IO11		0x1b0b0
> +				MX6QDL_PAD_SD2_DAT3__GPIO1_IO12		0x1b0b0
> +				MX6QDL_PAD_SD4_DAT4__GPIO2_IO12		0x1b0b0
> +				MX6QDL_PAD_SD4_DAT7__GPIO2_IO15		0x1b0b0
> +				MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14	0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_gpio_leds: gpioledsgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15
> 	0x80000000
> +			>;
> +		};
> +
> +		pinctrl_gpmi_nand: gpminandgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
> +				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
> +				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
> +				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
> +				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
> +				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
> +				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
> +				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
> +				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
> +				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
> +				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
> +				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
> +				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
> +				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
> +				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
> +				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
> +				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
> +			>;
> +		};
> +
> +		pinctrl_hdmi_cec: hdmicecgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE	0x1f8b0
> +			>;
> +		};
> +
> +		pinctrl_i2c2: i2c2grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_EIM_EB2__I2C2_SCL	0x4001b8b1
> +				MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
> +			>;
> +		};
> +
> +		pinctrl_i2c3: i2c3grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
> +				MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
> +			>;
> +		};
> +
> +		pinctrl_i2c3mux: i2c3muxgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
> +			>;
> +		};
> +
> +		pinctrl_ipu1_csi0: ipu1csi0grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
> +				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC
> 0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_max7310: max7310grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_pwm3: pwm1grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
> +			>;
> +		};
> +
> +		pinctrl_gpt_input_capture0: gptinputcapture0grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1	0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_gpt_input_capture1: gptinputcapture1grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2	0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_spdif: spdifgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_uart4: uart4grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
> +				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
> +			>;
> +		};
> +
> +		pinctrl_usbotg: usbotggrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
> +			>;
> +		};
> +
> +		pinctrl_usdhc3: usdhc3grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
> +				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
> +				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
> +				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
> +				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
> +				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
> +				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
> +				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
> +				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
> +				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
> +			>;
> +		};
> +
> +		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
> +				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
> +				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
> +				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
> +				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
> +				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
> +				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170b9
> +				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170b9
> +				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170b9
> +				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170b9
> +			>;
> +		};
> +
> +		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
> +				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
> +				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
> +				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
> +				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
> +				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
> +				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170f9
> +				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170f9
> +				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170f9
> +				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170f9
> +			>;
> +		};
> +
> +		pinctrl_weim_cs0: weimcs0grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_EIM_CS0__EIM_CS0_B		0xb0b1
> +			>;
> +		};
> +
> +		pinctrl_weim_nor: weimnorgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_EIM_OE__EIM_OE_B		0xb0b1
> +				MX6QDL_PAD_EIM_RW__EIM_RW		0xb0b1
> +				MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B		0xb060
> +				MX6QDL_PAD_EIM_D16__EIM_DATA16		0x1b0b0
> +				MX6QDL_PAD_EIM_D17__EIM_DATA17		0x1b0b0
> +				MX6QDL_PAD_EIM_D18__EIM_DATA18		0x1b0b0
> +				MX6QDL_PAD_EIM_D19__EIM_DATA19		0x1b0b0
> +				MX6QDL_PAD_EIM_D20__EIM_DATA20		0x1b0b0
> +				MX6QDL_PAD_EIM_D21__EIM_DATA21		0x1b0b0
> +				MX6QDL_PAD_EIM_D22__EIM_DATA22		0x1b0b0
> +				MX6QDL_PAD_EIM_D23__EIM_DATA23		0x1b0b0
> +				MX6QDL_PAD_EIM_D24__EIM_DATA24		0x1b0b0
> +				MX6QDL_PAD_EIM_D25__EIM_DATA25		0x1b0b0
> +				MX6QDL_PAD_EIM_D26__EIM_DATA26		0x1b0b0
> +				MX6QDL_PAD_EIM_D27__EIM_DATA27		0x1b0b0
> +				MX6QDL_PAD_EIM_D28__EIM_DATA28		0x1b0b0
> +				MX6QDL_PAD_EIM_D29__EIM_DATA29		0x1b0b0
> +				MX6QDL_PAD_EIM_D30__EIM_DATA30		0x1b0b0
> +				MX6QDL_PAD_EIM_D31__EIM_DATA31		0x1b0b0
> +				MX6QDL_PAD_EIM_A23__EIM_ADDR23		0xb0b1
> +				MX6QDL_PAD_EIM_A22__EIM_ADDR22		0xb0b1
> +				MX6QDL_PAD_EIM_A21__EIM_ADDR21		0xb0b1
> +				MX6QDL_PAD_EIM_A20__EIM_ADDR20		0xb0b1
> +				MX6QDL_PAD_EIM_A19__EIM_ADDR19		0xb0b1
> +				MX6QDL_PAD_EIM_A18__EIM_ADDR18		0xb0b1
> +				MX6QDL_PAD_EIM_A17__EIM_ADDR17		0xb0b1
> +				MX6QDL_PAD_EIM_A16__EIM_ADDR16		0xb0b1
> +				MX6QDL_PAD_EIM_DA15__EIM_AD15		0xb0b1
> +				MX6QDL_PAD_EIM_DA14__EIM_AD14		0xb0b1
> +				MX6QDL_PAD_EIM_DA13__EIM_AD13		0xb0b1
> +				MX6QDL_PAD_EIM_DA12__EIM_AD12		0xb0b1
> +				MX6QDL_PAD_EIM_DA11__EIM_AD11		0xb0b1
> +				MX6QDL_PAD_EIM_DA10__EIM_AD10		0xb0b1
> +				MX6QDL_PAD_EIM_DA9__EIM_AD09		0xb0b1
> +				MX6QDL_PAD_EIM_DA8__EIM_AD08		0xb0b1
> +				MX6QDL_PAD_EIM_DA7__EIM_AD07		0xb0b1
> +				MX6QDL_PAD_EIM_DA6__EIM_AD06		0xb0b1
> +				MX6QDL_PAD_EIM_DA5__EIM_AD05		0xb0b1
> +				MX6QDL_PAD_EIM_DA4__EIM_AD04		0xb0b1
> +				MX6QDL_PAD_EIM_DA3__EIM_AD03		0xb0b1
> +				MX6QDL_PAD_EIM_DA2__EIM_AD02		0xb0b1
> +				MX6QDL_PAD_EIM_DA1__EIM_AD01		0xb0b1
> +				MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0b1
> +			>;
> +		};
> +	};
> +};
> +
> +&ldb {
> +	status = "okay";
> +
> +	lvds-channel at 0 {
> +		fsl,data-mapping = "spwg";
> +		fsl,data-width = <18>;
> +		status = "okay";
> +
> +		display-timings {
> +			native-mode = <&timing0>;
> +			timing0: hsd100pxn1 {
> +				clock-frequency = <65000000>;
> +				hactive = <1024>;
> +				vactive = <768>;
> +				hback-porch = <220>;
> +				hfront-porch = <40>;
> +				vback-porch = <21>;
> +				vfront-porch = <7>;
> +				hsync-len = <60>;
> +				vsync-len = <10>;
> +			};
> +		};
> +	};
> +};
> +
> +&pwm3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_pwm3>;
> +	status = "okay";
> +};
> +
> +&spdif {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_spdif>;
> +	status = "okay";
> +};
> +
> +&uart4 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart4>;
> +	status = "okay";
> +};
> +
> +&usbh1 {
> +	vbus-supply = <&reg_usb_h1_vbus>;
> +	status = "okay";
> +};
> +
> +&usbotg {
> +	vbus-supply = <&reg_usb_otg_vbus>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usbotg>;
> +	status = "okay";
> +};
> +
> +&usdhc3 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc3>;
> +	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> +	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> +	cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
> +	wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&weim {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
> +	ranges = <0 0 0x08000000 0x08000000>;
> +	status = "disabled"; /* pin conflict with SPI NOR */
> +
> +	nor at 0,0 {
> +		compatible = "cfi-flash";
> +		reg = <0 0 0x02000000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		bank-width = <2>;
> +		fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
> +				0x0000c000 0x1404a38e 0x00000000>;
> +	};
> +};
> diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi
> b/arch/arm/dts/imx6qdl-sabresd.dtsi
> new file mode 100644
> index 0000000..2cd5a9f
> --- /dev/null
> +++ b/arch/arm/dts/imx6qdl-sabresd.dtsi
> @@ -0,0 +1,741 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +//
> +// Copyright 2012 Freescale Semiconductor, Inc.
> +// Copyright 2011 Linaro Ltd.
> +
> +#include <dt-bindings/clock/imx6qdl-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> +	aliases {
> +		mmc1 = &usdhc3;
> +	};
> +
> +	chosen {
> +		stdout-path = &uart1;
> +	};
> +
> +	memory at 10000000 {
> +		reg = <0x10000000 0x40000000>;
> +	};
> +
> +	regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		reg_usb_otg_vbus: regulator at 0 {
> +			compatible = "regulator-fixed";
> +			reg = <0>;
> +			regulator-name = "usb_otg_vbus";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&gpio3 22 0>;
> +			enable-active-high;
> +			vin-supply = <&swbst_reg>;
> +		};
> +
> +		reg_usb_h1_vbus: regulator at 1 {
> +			compatible = "regulator-fixed";
> +			reg = <1>;
> +			regulator-name = "usb_h1_vbus";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&gpio1 29 0>;
> +			enable-active-high;
> +			vin-supply = <&swbst_reg>;
> +		};
> +
> +		reg_audio: regulator at 2 {
> +			compatible = "regulator-fixed";
> +			reg = <2>;
> +			regulator-name = "wm8962-supply";
> +			gpio = <&gpio4 10 0>;
> +			enable-active-high;
> +		};
> +
> +		reg_pcie: regulator at 3 {
> +			compatible = "regulator-fixed";
> +			reg = <3>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&pinctrl_pcie_reg>;
> +			regulator-name = "MPCIE_3V3";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			gpio = <&gpio3 19 0>;
> +			enable-active-high;
> +		};
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_gpio_keys>;
> +
> +		power {
> +			label = "Power Button";
> +			gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +			linux,code = <KEY_POWER>;
> +		};
> +
> +		volume-up {
> +			label = "Volume Up";
> +			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +			linux,code = <KEY_VOLUMEUP>;
> +		};
> +
> +		volume-down {
> +			label = "Volume Down";
> +			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +			linux,code = <KEY_VOLUMEDOWN>;
> +		};
> +	};
> +
> +	sound {
> +		compatible = "fsl,imx6q-sabresd-wm8962",
> +			   "fsl,imx-audio-wm8962";
> +		model = "wm8962-audio";
> +		ssi-controller = <&ssi2>;
> +		audio-codec = <&codec>;
> +		audio-routing =
> +			"Headphone Jack", "HPOUTL",
> +			"Headphone Jack", "HPOUTR",
> +			"Ext Spk", "SPKOUTL",
> +			"Ext Spk", "SPKOUTR",
> +			"AMIC", "MICBIAS",
> +			"IN3R", "AMIC";
> +		mux-int-port = <2>;
> +		mux-ext-port = <3>;
> +	};
> +
> +	backlight_lvds: backlight-lvds {
> +		compatible = "pwm-backlight";
> +		pwms = <&pwm1 0 5000000>;
> +		brightness-levels = <0 4 8 16 32 64 128 255>;
> +		default-brightness-level = <7>;
> +		status = "okay";
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_gpio_leds>;
> +
> +		red {
> +			gpios = <&gpio1 2 0>;
> +			default-state = "on";
> +		};
> +	};
> +
> +	panel {
> +		compatible = "hannstar,hsd100pxn1";
> +		backlight = <&backlight_lvds>;
> +
> +		port {
> +			panel_in: endpoint {
> +				remote-endpoint = <&lvds0_out>;
> +			};
> +		};
> +	};
> +};
> +
> +&ipu1_csi0_from_ipu1_csi0_mux {
> +	bus-width = <8>;
> +	data-shift = <12>; /* Lines 19:12 used */
> +	hsync-active = <1>;
> +	vsync-active = <1>;
> +};
> +
> +&ipu1_csi0_mux_from_parallel_sensor {
> +	remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
> +};
> +
> +&ipu1_csi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ipu1_csi0>;
> +};
> +
> +&mipi_csi {
> +	status = "okay";
> +
> +	port at 0 {
> +		reg = <0>;
> +
> +		mipi_csi2_in: endpoint {
> +			remote-endpoint = <&ov5640_to_mipi_csi2>;
> +			clock-lanes = <0>;
> +			data-lanes = <1 2>;
> +		};
> +	};
> +};
> +
> +&audmux {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_audmux>;
> +	status = "okay";
> +};
> +
> +&clks {
> +	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
> +			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
> +	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
> +				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
> +};
> +
> +&ecspi1 {
> +	cs-gpios = <&gpio4 9 0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ecspi1>;
> +	status = "okay";
> +
> +	flash: m25p80 at 0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "st,m25p32", "jedec,spi-nor";
> +		spi-max-frequency = <20000000>;
> +		reg = <0>;
> +	};
> +};
> +
> +&fec {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_enet>;
> +	phy-mode = "rgmii";
> +	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
> +	status = "okay";
> +};
> +
> +&hdmi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hdmi_cec>;
> +	ddc-i2c-bus = <&i2c2>;
> +	status = "okay";
> +};
> +
> +&i2c1 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c1>;
> +	status = "okay";
> +
> +	codec: wm8962 at 1a {
> +		compatible = "wlf,wm8962";
> +		reg = <0x1a>;
> +		clocks = <&clks IMX6QDL_CLK_CKO>;
> +		DCVDD-supply = <&reg_audio>;
> +		DBVDD-supply = <&reg_audio>;
> +		AVDD-supply = <&reg_audio>;
> +		CPVDD-supply = <&reg_audio>;
> +		MICVDD-supply = <&reg_audio>;
> +		PLLVDD-supply = <&reg_audio>;
> +		SPKVDD1-supply = <&reg_audio>;
> +		SPKVDD2-supply = <&reg_audio>;
> +		gpio-cfg = <
> +			0x0000 /* 0:Default */
> +			0x0000 /* 1:Default */
> +			0x0013 /* 2:FN_DMICCLK */
> +			0x0000 /* 3:Default */
> +			0x8014 /* 4:FN_DMICCDAT */
> +			0x0000 /* 5:Default */
> +		>;
> +	};
> +
> +	ov5642: camera at 3c {
> +		compatible = "ovti,ov5642";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_ov5642>;
> +		clocks = <&clks IMX6QDL_CLK_CKO>;
> +		clock-names = "xclk";
> +		reg = <0x3c>;
> +		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
> +		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
> +						rev B board is VGEN5 */
> +		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
> +		powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
> +		reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
> +		status = "disabled";
> +
> +		port {
> +			ov5642_to_ipu1_csi0_mux: endpoint {
> +				remote-endpoint =
> <&ipu1_csi0_mux_from_parallel_sensor>;
> +				bus-width = <8>;
> +				hsync-active = <1>;
> +				vsync-active = <1>;
> +			};
> +		};
> +	};
> +};
> +
> +&i2c2 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c2>;
> +	status = "okay";
> +
> +	ov5640: camera at 3c {
> +		compatible = "ovti,ov5640";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_ov5640>;
> +		reg = <0x3c>;
> +		clocks = <&clks IMX6QDL_CLK_CKO>;
> +		clock-names = "xclk";
> +		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
> +		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
> +						rev B board is VGEN5 */
> +		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
> +		powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
> +		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
> +
> +		port {
> +			ov5640_to_mipi_csi2: endpoint {
> +				remote-endpoint = <&mipi_csi2_in>;
> +				clock-lanes = <0>;
> +				data-lanes = <1 2>;
> +			};
> +		};
> +	};
> +
> +	pmic: pfuze100 at 8 {
> +		compatible = "fsl,pfuze100";
> +		reg = <0x08>;
> +
> +		regulators {
> +			sw1a_reg: sw1ab {
> +				regulator-min-microvolt = <300000>;
> +				regulator-max-microvolt = <1875000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <6250>;
> +			};
> +
> +			sw1c_reg: sw1c {
> +				regulator-min-microvolt = <300000>;
> +				regulator-max-microvolt = <1875000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <6250>;
> +			};
> +
> +			sw2_reg: sw2 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <6250>;
> +			};
> +
> +			sw3a_reg: sw3a {
> +				regulator-min-microvolt = <400000>;
> +				regulator-max-microvolt = <1975000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			sw3b_reg: sw3b {
> +				regulator-min-microvolt = <400000>;
> +				regulator-max-microvolt = <1975000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			sw4_reg: sw4 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-always-on;
> +			};
> +
> +			swbst_reg: swbst {
> +				regulator-min-microvolt = <5000000>;
> +				regulator-max-microvolt = <5150000>;
> +			};
> +
> +			snvs_reg: vsnvs {
> +				regulator-min-microvolt = <1000000>;
> +				regulator-max-microvolt = <3000000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			vref_reg: vrefddr {
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			vgen1_reg: vgen1 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <1550000>;
> +			};
> +
> +			vgen2_reg: vgen2 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <1550000>;
> +			};
> +
> +			vgen3_reg: vgen3 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +			};
> +
> +			vgen4_reg: vgen4 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-always-on;
> +			};
> +
> +			vgen5_reg: vgen5 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-always-on;
> +			};
> +
> +			vgen6_reg: vgen6 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-always-on;
> +			};
> +		};
> +	};
> +};
> +
> +&i2c3 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c3>;
> +	status = "okay";
> +
> +	egalax_ts at 4 {
> +		compatible = "eeti,egalax_ts";
> +		reg = <0x04>;
> +		interrupt-parent = <&gpio6>;
> +		interrupts = <7 2>;
> +		wakeup-gpios = <&gpio6 7 0>;
> +	};
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hog>;
> +
> +	imx6qdl-sabresd {
> +		pinctrl_hog: hoggrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
> +				MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
> +				MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
> +				MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
> +				MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
> +				MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
> +				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
> +				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0
> +				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_audmux: audmuxgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
> +				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
> +				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
> +				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
> +			>;
> +		};
> +
> +		pinctrl_ecspi1: ecspi1grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_KEY_COL1__ECSPI1_MISO	0x100b1
> +				MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI	0x100b1
> +				MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK	0x100b1
> +				MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_enet: enetgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
> +				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
> +				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
> +				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
> +				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
> +				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
> +				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
> +				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
> +				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
> +				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
> +				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
> +				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
> +				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
> +				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
> +				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL
> 	0x1b030
> +				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
> +			>;
> +		};
> +
> +		pinctrl_gpio_keys: gpio_keysgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
> +				MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1b0b0
> +				MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_hdmi_cec: hdmicecgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE
> 	0x1f8b0
> +			>;
> +		};
> +
> +		pinctrl_i2c1: i2c1grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA
> 	0x4001b8b1
> +				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
> +			>;
> +		};
> +
> +		pinctrl_i2c2: i2c2grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
> +				MX6QDL_PAD_KEY_ROW3__I2C2_SDA
> 	0x4001b8b1
> +			>;
> +		};
> +
> +		pinctrl_i2c3: i2c3grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
> +				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
> +			>;
> +		};
> +
> +		pinctrl_ipu1_csi0: ipu1csi0grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC
> 0x1b0b0
> +				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC
> 0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_ov5640: ov5640grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
> +				MX6QDL_PAD_SD1_CLK__GPIO1_IO20  0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_ov5642: ov5642grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
> +				MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_pcie: pciegrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_GPIO_17__GPIO7_IO12	0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_pcie_reg: pciereggrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_EIM_D19__GPIO3_IO19	0x1b0b0
> +			>;
> +		};
> +
> +		pinctrl_pwm1: pwm1grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
> +			>;
> +		};
> +
> +		pinctrl_uart1: uart1grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
> +				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
> +			>;
> +		};
> +
> +		pinctrl_usbotg: usbotggrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
> +			>;
> +		};
> +
> +		pinctrl_usdhc2: usdhc2grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
> +				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
> +				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
> +				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
> +				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
> +				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
> +				MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
> +				MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
> +				MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
> +				MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
> +			>;
> +		};
> +
> +		pinctrl_usdhc3: usdhc3grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
> +				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
> +				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
> +				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
> +				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
> +				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
> +				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
> +				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
> +				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
> +				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
> +			>;
> +		};
> +
> +		pinctrl_usdhc4: usdhc4grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
> +				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
> +				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
> +				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
> +				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
> +				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
> +				MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
> +				MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
> +				MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
> +				MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
> +			>;
> +		};
> +
> +		pinctrl_wdog: wdoggrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_GPIO_1__WDOG2_B		0x1b0b0
> +			>;
> +		};
> +	};
> +
> +	gpio_leds {
> +		pinctrl_gpio_leds: gpioledsgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
> +			>;
> +		};
> +	};
> +};
> +
> +&ldb {
> +	status = "okay";
> +
> +	lvds-channel at 1 {
> +		fsl,data-mapping = "spwg";
> +		fsl,data-width = <18>;
> +		status = "okay";
> +
> +		port at 4 {
> +			reg = <4>;
> +
> +			lvds0_out: endpoint {
> +				remote-endpoint = <&panel_in>;
> +			};
> +		};
> +	};
> +};
> +
> +&pcie {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_pcie>;
> +	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
> +	vpcie-supply = <&reg_pcie>;
> +	status = "okay";
> +};
> +
> +&pwm1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_pwm1>;
> +	status = "okay";
> +};
> +
> +&reg_arm {
> +       vin-supply = <&sw1a_reg>;
> +};
> +
> +&reg_pu {
> +       vin-supply = <&sw1c_reg>;
> +};
> +
> +&reg_soc {
> +       vin-supply = <&sw1c_reg>;
> +};
> +
> +&snvs_poweroff {
> +	status = "okay";
> +};
> +
> +&ssi2 {
> +	status = "okay";
> +};
> +
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1>;
> +	status = "okay";
> +};
> +
> +&usbh1 {
> +	vbus-supply = <&reg_usb_h1_vbus>;
> +	status = "okay";
> +};
> +
> +&usbotg {
> +	vbus-supply = <&reg_usb_otg_vbus>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usbotg>;
> +	disable-over-current;
> +	status = "okay";
> +};
> +
> +&usdhc2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usdhc2>;
> +	bus-width = <8>;
> +	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
> +	wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&usdhc3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usdhc3>;
> +	bus-width = <8>;
> +	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
> +	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&usdhc4 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usdhc4>;
> +	bus-width = <8>;
> +	non-removable;
> +	no-1-8-v;
> +	status = "okay";
> +};
> +
> +&wdog1 {
> +	status = "disabled";
> +};
> +
> +&wdog2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_wdog>;
> +	fsl,ext-reset-output;
> +	status = "okay";
> +};
> diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
> index b13b0b2..e4daf15 100644
> --- a/arch/arm/dts/imx6qdl.dtsi
> +++ b/arch/arm/dts/imx6qdl.dtsi
> @@ -1,21 +1,23 @@
> -/*
> - * Copyright 2011 Freescale Semiconductor, Inc.
> - * Copyright 2011 Linaro Ltd.
> - *
> - * The code contained herein is licensed under the GNU General Public
> - * License. You may obtain a copy of the GNU General Public License
> - * Version 2 or later at the following locations:
> - *
> - * http://www.opensource.org/licenses/gpl-license.html
> - * http://www.gnu.org/copyleft/gpl.html
> - */
> +// SPDX-License-Identifier: GPL-2.0+
> +//
> +// Copyright 2011 Freescale Semiconductor, Inc.
> +// Copyright 2011 Linaro Ltd.
> 
>  #include <dt-bindings/clock/imx6qdl-clock.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> 
> -#include "skeleton.dtsi"
> -
>  / {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	/*
> +	 * The decompressor and also some bootloaders rely on a
> +	 * pre-existing /chosen node to be available to insert the
> +	 * command line and merge other ATAGS info.
> +	 * Also for U-Boot there must be a pre-existing /memory node.
> +	 */
> +	chosen {};
> +	memory { device_type = "memory"; };
> +
>  	aliases {
>  		ethernet0 = &fec;
>  		can0 = &can1;
> @@ -49,9 +51,6 @@
>  	};
> 
>  	clocks {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -
>  		ckil {
>  			compatible = "fsl,imx-ckil", "fixed-clock";
>  			#clock-cells = <0>;
> @@ -71,6 +70,75 @@
>  		};
>  	};
> 
> +	tempmon: tempmon {
> +		compatible = "fsl,imx6q-tempmon";
> +		interrupt-parent = <&gpc>;
> +		interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
> +		fsl,tempmon = <&anatop>;
> +		fsl,tempmon-data = <&ocotp>;
> +		clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
> +	};
> +
> +	ldb: ldb {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
> +		gpr = <&gpr>;
> +		status = "disabled";
> +
> +		lvds-channel at 0 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0>;
> +			status = "disabled";
> +
> +			port at 0 {
> +				reg = <0>;
> +
> +				lvds0_mux_0: endpoint {
> +					remote-endpoint = <&ipu1_di0_lvds0>;
> +				};
> +			};
> +
> +			port at 1 {
> +				reg = <1>;
> +
> +				lvds0_mux_1: endpoint {
> +					remote-endpoint = <&ipu1_di1_lvds0>;
> +				};
> +			};
> +		};
> +
> +		lvds-channel at 1 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <1>;
> +			status = "disabled";
> +
> +			port at 0 {
> +				reg = <0>;
> +
> +				lvds1_mux_0: endpoint {
> +					remote-endpoint = <&ipu1_di0_lvds1>;
> +				};
> +			};
> +
> +			port at 1 {
> +				reg = <1>;
> +
> +				lvds1_mux_1: endpoint {
> +					remote-endpoint = <&ipu1_di1_lvds1>;
> +				};
> +			};
> +		};
> +	};
> +
> +	pmu: pmu {
> +		compatible = "arm,cortex-a9-pmu";
> +		interrupt-parent = <&gpc>;
> +		interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
>  	soc {
>  		#address-cells = <1>;
>  		#size-cells = <1>;
> @@ -78,7 +146,7 @@
>  		interrupt-parent = <&gpc>;
>  		ranges;
> 
> -		dma_apbh: dma-apbh at 00110000 {
> +		dma_apbh: dma-apbh at 110000 {
>  			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
>  			reg = <0x00110000 0x2000>;
>  			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
> @@ -91,7 +159,7 @@
>  			clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
>  		};
> 
> -		gpmi: gpmi-nand at 00112000 {
> +		gpmi: gpmi-nand at 112000 {
>  			compatible = "fsl,imx6q-gpmi-nand";
>  			#address-cells = <1>;
>  			#size-cells = <1>;
> @@ -111,7 +179,7 @@
>  			status = "disabled";
>  		};
> 
> -		hdmi: hdmi at 0120000 {
> +		hdmi: hdmi at 120000 {
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			reg = <0x00120000 0x9000>;
> @@ -139,7 +207,7 @@
>  			};
>  		};
> 
> -		gpu_3d: gpu at 00130000 {
> +		gpu_3d: gpu at 130000 {
>  			compatible = "vivante,gc";
>  			reg = <0x00130000 0x4000>;
>  			interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
> @@ -147,20 +215,20 @@
>  				 <&clks IMX6QDL_CLK_GPU3D_CORE>,
>  				 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
>  			clock-names = "bus", "core", "shader";
> -			power-domains = <&gpc 1>;
> +			power-domains = <&pd_pu>;
>  		};
> 
> -		gpu_2d: gpu at 00134000 {
> +		gpu_2d: gpu at 134000 {
>  			compatible = "vivante,gc";
>  			reg = <0x00134000 0x4000>;
>  			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
>  				 <&clks IMX6QDL_CLK_GPU2D_CORE>;
>  			clock-names = "bus", "core";
> -			power-domains = <&gpc 1>;
> +			power-domains = <&pd_pu>;
>  		};
> 
> -		timer at 00a00600 {
> +		timer at a00600 {
>  			compatible = "arm,cortex-a9-twd-timer";
>  			reg = <0x00a00600 0x20>;
>  			interrupts = <1 13 0xf01>;
> @@ -168,7 +236,7 @@
>  			clocks = <&clks IMX6QDL_CLK_TWD>;
>  		};
> 
> -		intc: interrupt-controller at 00a01000 {
> +		intc: interrupt-controller at a01000 {
>  			compatible = "arm,cortex-a9-gic";
>  			#interrupt-cells = <3>;
>  			interrupt-controller;
> @@ -177,7 +245,7 @@
>  			interrupt-parent = <&intc>;
>  		};
> 
> -		L2: l2-cache at 00a02000 {
> +		L2: l2-cache at a02000 {
>  			compatible = "arm,pl310-cache";
>  			reg = <0x00a02000 0x1000>;
>  			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
> @@ -188,7 +256,7 @@
>  			arm,shared-override;
>  		};
> 
> -		pcie: pcie at 0x01000000 {
> +		pcie: pcie at 1ffc000 {
>  			compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
>  			reg = <0x01ffc000 0x04000>,
>  			      <0x01f00000 0x80000>;
> @@ -196,6 +264,7 @@
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> +			bus-range = <0x00 0xff>;
>  			ranges = <0x81000000 0 0          0x01f80000 0
> 0x00010000 /* downstream I/O */
>  				  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
> /* non-prefetchable memory */
>  			num-lanes = <1>;
> @@ -204,9 +273,9 @@
>  			#interrupt-cells = <1>;
>  			interrupt-map-mask = <0 0 0 0x7>;
>  			interrupt-map = <0 0 0 1 &gpc GIC_SPI 123
> IRQ_TYPE_LEVEL_HIGH>,
> -			                <0 0 0 2 &gpc GIC_SPI 122
> IRQ_TYPE_LEVEL_HIGH>,
> -			                <0 0 0 3 &gpc GIC_SPI 121
> IRQ_TYPE_LEVEL_HIGH>,
> -			                <0 0 0 4 &gpc GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>;
> +					<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
>  				 <&clks IMX6QDL_CLK_LVDS1_GATE>,
>  				 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
> @@ -214,26 +283,21 @@
>  			status = "disabled";
>  		};
> 
> -		pmu {
> -			compatible = "arm,cortex-a9-pmu";
> -			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
> -		};
> -
> -		aips-bus at 02000000 { /* AIPS1 */
> +		aips-bus at 2000000 { /* AIPS1 */
>  			compatible = "fsl,aips-bus", "simple-bus";
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			reg = <0x02000000 0x100000>;
>  			ranges;
> 
> -			spba-bus at 02000000 {
> +			spba-bus at 2000000 {
>  				compatible = "fsl,spba-bus", "simple-bus";
>  				#address-cells = <1>;
>  				#size-cells = <1>;
>  				reg = <0x02000000 0x40000>;
>  				ranges;
> 
> -				spdif: spdif at 02004000 {
> +				spdif: spdif at 2004000 {
>  					compatible = "fsl,imx35-spdif";
>  					reg = <0x02004000 0x4000>;
>  					interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
> @@ -253,7 +317,7 @@
>  					status = "disabled";
>  				};
> 
> -				ecspi1: ecspi at 02008000 {
> +				ecspi1: spi at 2008000 {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
>  					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
> @@ -267,7 +331,7 @@
>  					status = "disabled";
>  				};
> 
> -				ecspi2: ecspi at 0200c000 {
> +				ecspi2: spi at 200c000 {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
>  					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
> @@ -281,7 +345,7 @@
>  					status = "disabled";
>  				};
> 
> -				ecspi3: ecspi at 02010000 {
> +				ecspi3: spi at 2010000 {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
>  					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
> @@ -295,7 +359,7 @@
>  					status = "disabled";
>  				};
> 
> -				ecspi4: ecspi at 02014000 {
> +				ecspi4: spi at 2014000 {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
>  					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
> @@ -309,7 +373,7 @@
>  					status = "disabled";
>  				};
> 
> -				uart1: serial at 02020000 {
> +				uart1: serial at 2020000 {
>  					compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>  					reg = <0x02020000 0x4000>;
>  					interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
> @@ -321,7 +385,7 @@
>  					status = "disabled";
>  				};
> 
> -				esai: esai at 02024000 {
> +				esai: esai at 2024000 {
>  					#sound-dai-cells = <0>;
>  					compatible = "fsl,imx35-esai";
>  					reg = <0x02024000 0x4000>;
> @@ -337,7 +401,7 @@
>  					status = "disabled";
>  				};
> 
> -				ssi1: ssi at 02028000 {
> +				ssi1: ssi at 2028000 {
>  					#sound-dai-cells = <0>;
>  					compatible = "fsl,imx6q-ssi",
>  							"fsl,imx51-ssi";
> @@ -353,7 +417,7 @@
>  					status = "disabled";
>  				};
> 
> -				ssi2: ssi at 0202c000 {
> +				ssi2: ssi at 202c000 {
>  					#sound-dai-cells = <0>;
>  					compatible = "fsl,imx6q-ssi",
>  							"fsl,imx51-ssi";
> @@ -369,7 +433,7 @@
>  					status = "disabled";
>  				};
> 
> -				ssi3: ssi at 02030000 {
> +				ssi3: ssi at 2030000 {
>  					#sound-dai-cells = <0>;
>  					compatible = "fsl,imx6q-ssi",
>  							"fsl,imx51-ssi";
> @@ -385,7 +449,7 @@
>  					status = "disabled";
>  				};
> 
> -				asrc: asrc at 02034000 {
> +				asrc: asrc at 2034000 {
>  					compatible = "fsl,imx53-asrc";
>  					reg = <0x02034000 0x4000>;
>  					interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
> @@ -410,12 +474,12 @@
>  					status = "okay";
>  				};
> 
> -				spba at 0203c000 {
> +				spba at 203c000 {
>  					reg = <0x0203c000 0x4000>;
>  				};
>  			};
> 
> -			vpu: vpu at 02040000 {
> +			vpu: vpu at 2040000 {
>  				compatible = "cnm,coda960";
>  				reg = <0x02040000 0x3c000>;
>  				interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
> @@ -424,16 +488,16 @@
>  				clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
>  					 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
>  				clock-names = "per", "ahb";
> -				power-domains = <&gpc 1>;
> +				power-domains = <&pd_pu>;
>  				resets = <&src 1>;
>  				iram = <&ocram>;
>  			};
> 
> -			aipstz at 0207c000 { /* AIPSTZ1 */
> +			aipstz at 207c000 { /* AIPSTZ1 */
>  				reg = <0x0207c000 0x4000>;
>  			};
> 
> -			pwm1: pwm at 02080000 {
> +			pwm1: pwm at 2080000 {
>  				#pwm-cells = <2>;
>  				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
>  				reg = <0x02080000 0x4000>;
> @@ -444,7 +508,7 @@
>  				status = "disabled";
>  			};
> 
> -			pwm2: pwm at 02084000 {
> +			pwm2: pwm at 2084000 {
>  				#pwm-cells = <2>;
>  				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
>  				reg = <0x02084000 0x4000>;
> @@ -455,7 +519,7 @@
>  				status = "disabled";
>  			};
> 
> -			pwm3: pwm at 02088000 {
> +			pwm3: pwm at 2088000 {
>  				#pwm-cells = <2>;
>  				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
>  				reg = <0x02088000 0x4000>;
> @@ -466,7 +530,7 @@
>  				status = "disabled";
>  			};
> 
> -			pwm4: pwm at 0208c000 {
> +			pwm4: pwm at 208c000 {
>  				#pwm-cells = <2>;
>  				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
>  				reg = <0x0208c000 0x4000>;
> @@ -477,7 +541,7 @@
>  				status = "disabled";
>  			};
> 
> -			can1: flexcan at 02090000 {
> +			can1: flexcan at 2090000 {
>  				compatible = "fsl,imx6q-flexcan";
>  				reg = <0x02090000 0x4000>;
>  				interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
> @@ -487,7 +551,7 @@
>  				status = "disabled";
>  			};
> 
> -			can2: flexcan at 02094000 {
> +			can2: flexcan at 2094000 {
>  				compatible = "fsl,imx6q-flexcan";
>  				reg = <0x02094000 0x4000>;
>  				interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
> @@ -497,7 +561,7 @@
>  				status = "disabled";
>  			};
> 
> -			gpt: gpt at 02098000 {
> +			gpt: gpt at 2098000 {
>  				compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
>  				reg = <0x02098000 0x4000>;
>  				interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
> @@ -507,7 +571,7 @@
>  				clock-names = "ipg", "per", "osc_per";
>  			};
> 
> -			gpio1: gpio at 0209c000 {
> +			gpio1: gpio at 209c000 {
>  				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
>  				reg = <0x0209c000 0x4000>;
>  				interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
> @@ -518,7 +582,7 @@
>  				#interrupt-cells = <2>;
>  			};
> 
> -			gpio2: gpio at 020a0000 {
> +			gpio2: gpio at 20a0000 {
>  				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
>  				reg = <0x020a0000 0x4000>;
>  				interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
> @@ -529,7 +593,7 @@
>  				#interrupt-cells = <2>;
>  			};
> 
> -			gpio3: gpio at 020a4000 {
> +			gpio3: gpio at 20a4000 {
>  				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
>  				reg = <0x020a4000 0x4000>;
>  				interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
> @@ -540,7 +604,7 @@
>  				#interrupt-cells = <2>;
>  			};
> 
> -			gpio4: gpio at 020a8000 {
> +			gpio4: gpio at 20a8000 {
>  				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
>  				reg = <0x020a8000 0x4000>;
>  				interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
> @@ -551,7 +615,7 @@
>  				#interrupt-cells = <2>;
>  			};
> 
> -			gpio5: gpio at 020ac000 {
> +			gpio5: gpio at 20ac000 {
>  				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
>  				reg = <0x020ac000 0x4000>;
>  				interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
> @@ -562,7 +626,7 @@
>  				#interrupt-cells = <2>;
>  			};
> 
> -			gpio6: gpio at 020b0000 {
> +			gpio6: gpio at 20b0000 {
>  				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
>  				reg = <0x020b0000 0x4000>;
>  				interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
> @@ -573,7 +637,7 @@
>  				#interrupt-cells = <2>;
>  			};
> 
> -			gpio7: gpio at 020b4000 {
> +			gpio7: gpio at 20b4000 {
>  				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
>  				reg = <0x020b4000 0x4000>;
>  				interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
> @@ -584,7 +648,7 @@
>  				#interrupt-cells = <2>;
>  			};
> 
> -			kpp: kpp at 020b8000 {
> +			kpp: kpp at 20b8000 {
>  				compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
>  				reg = <0x020b8000 0x4000>;
>  				interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
> @@ -592,14 +656,14 @@
>  				status = "disabled";
>  			};
> 
> -			wdog1: wdog at 020bc000 {
> +			wdog1: wdog at 20bc000 {
>  				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
>  				reg = <0x020bc000 0x4000>;
>  				interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
>  				clocks = <&clks IMX6QDL_CLK_DUMMY>;
>  			};
> 
> -			wdog2: wdog at 020c0000 {
> +			wdog2: wdog at 20c0000 {
>  				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
>  				reg = <0x020c0000 0x4000>;
>  				interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
> @@ -607,7 +671,7 @@
>  				status = "disabled";
>  			};
> 
> -			clks: ccm at 020c4000 {
> +			clks: ccm at 20c4000 {
>  				compatible = "fsl,imx6q-ccm";
>  				reg = <0x020c4000 0x4000>;
>  				interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
> @@ -615,7 +679,7 @@
>  				#clock-cells = <1>;
>  			};
> 
> -			anatop: anatop at 020c8000 {
> +			anatop: anatop at 20c8000 {
>  				compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
>  				reg = <0x020c8000 0x1000>;
>  				interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
> @@ -625,8 +689,8 @@
>  				regulator-1p1 {
>  					compatible = "fsl,anatop-regulator";
>  					regulator-name = "vdd1p1";
> -					regulator-min-microvolt = <800000>;
> -					regulator-max-microvolt = <1375000>;
> +					regulator-min-microvolt = <1000000>;
> +					regulator-max-microvolt = <1200000>;
>  					regulator-always-on;
>  					anatop-reg-offset = <0x110>;
>  					anatop-vol-bit-shift = <8>;
> @@ -634,6 +698,7 @@
>  					anatop-min-bit-val = <4>;
>  					anatop-min-voltage = <800000>;
>  					anatop-max-voltage = <1375000>;
> +					anatop-enable-bit = <0>;
>  				};
> 
>  				regulator-3p0 {
> @@ -648,20 +713,22 @@
>  					anatop-min-bit-val = <0>;
>  					anatop-min-voltage = <2625000>;
>  					anatop-max-voltage = <3400000>;
> +					anatop-enable-bit = <0>;
>  				};
> 
>  				regulator-2p5 {
>  					compatible = "fsl,anatop-regulator";
>  					regulator-name = "vdd2p5";
> -					regulator-min-microvolt = <2000000>;
> +					regulator-min-microvolt = <2250000>;
>  					regulator-max-microvolt = <2750000>;
>  					regulator-always-on;
>  					anatop-reg-offset = <0x130>;
>  					anatop-vol-bit-shift = <8>;
>  					anatop-vol-bit-width = <5>;
>  					anatop-min-bit-val = <0>;
> -					anatop-min-voltage = <2000000>;
> -					anatop-max-voltage = <2750000>;
> +					anatop-min-voltage = <2100000>;
> +					anatop-max-voltage = <2875000>;
> +					anatop-enable-bit = <0>;
>  				};
> 
>  				reg_arm: regulator-vddcore {
> @@ -716,15 +783,7 @@
>  				};
>  			};
> 
> -			tempmon: tempmon {
> -				compatible = "fsl,imx6q-tempmon";
> -				interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
> -				fsl,tempmon = <&anatop>;
> -				fsl,tempmon-data = <&ocotp>;
> -				clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
> -			};
> -
> -			usbphy1: usbphy at 020c9000 {
> +			usbphy1: usbphy at 20c9000 {
>  				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
>  				reg = <0x020c9000 0x1000>;
>  				interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
> @@ -732,7 +791,7 @@
>  				fsl,anatop = <&anatop>;
>  			};
> 
> -			usbphy2: usbphy at 020ca000 {
> +			usbphy2: usbphy at 20ca000 {
>  				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
>  				reg = <0x020ca000 0x1000>;
>  				interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
> @@ -740,7 +799,7 @@
>  				fsl,anatop = <&anatop>;
>  			};
> 
> -			snvs: snvs at 020cc000 {
> +			snvs: snvs at 20cc000 {
>  				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
>  				reg = <0x020cc000 0x4000>;
> 
> @@ -756,22 +815,27 @@
>  					compatible = "syscon-poweroff";
>  					regmap = <&snvs>;
>  					offset = <0x38>;
> +					value = <0x60>;
>  					mask = <0x60>;
>  					status = "disabled";
>  				};
> +
> +				snvs_lpgpr: snvs-lpgpr {
> +					compatible = "fsl,imx6q-snvs-lpgpr";
> +				};
>  			};
> 
> -			epit1: epit at 020d0000 { /* EPIT1 */
> +			epit1: epit at 20d0000 { /* EPIT1 */
>  				reg = <0x020d0000 0x4000>;
>  				interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
>  			};
> 
> -			epit2: epit at 020d4000 { /* EPIT2 */
> +			epit2: epit at 20d4000 { /* EPIT2 */
>  				reg = <0x020d4000 0x4000>;
>  				interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
>  			};
> 
> -			src: src at 020d8000 {
> +			src: src at 20d8000 {
>  				compatible = "fsl,imx6q-src", "fsl,imx51-src";
>  				reg = <0x020d8000 0x4000>;
>  				interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
> @@ -779,7 +843,7 @@
>  				#reset-cells = <1>;
>  			};
> 
> -			gpc: gpc at 020dc000 {
> +			gpc: gpc at 20dc000 {
>  				compatible = "fsl,imx6q-gpc";
>  				reg = <0x020dc000 0x4000>;
>  				interrupt-controller;
> @@ -787,91 +851,57 @@
>  				interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
>  					     <0 90 IRQ_TYPE_LEVEL_HIGH>;
>  				interrupt-parent = <&intc>;
> -				pu-supply = <&reg_pu>;
> -				clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
> -					 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
> -					 <&clks IMX6QDL_CLK_GPU2D_CORE>,
> -					 <&clks IMX6QDL_CLK_GPU2D_AXI>,
> -					 <&clks IMX6QDL_CLK_OPENVG_AXI>,
> -					 <&clks IMX6QDL_CLK_VPU_AXI>;
> -				#power-domain-cells = <1>;
> -			};
> -
> -			gpr: iomuxc-gpr at 020e0000 {
> -				compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
> -				reg = <0x020e0000 0x38>;
> -			};
> -
> -			iomuxc: iomuxc at 020e0000 {
> -				compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
> -				reg = <0x020e0000 0x4000>;
> -			};
> -
> -			ldb: ldb at 020e0008 {
> -				#address-cells = <1>;
> -				#size-cells = <0>;
> -				compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
> -				gpr = <&gpr>;
> -				status = "disabled";
> +				clocks = <&clks IMX6QDL_CLK_IPG>;
> +				clock-names = "ipg";
> 
> -				lvds-channel at 0 {
> +				pgc {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
> -					reg = <0>;
> -					status = "disabled";
> 
> -					port at 0 {
> +					power-domain at 0 {
>  						reg = <0>;
> -
> -						lvds0_mux_0: endpoint {
> -							remote-endpoint = <&ipu1_di0_lvds0>;
> -						};
> +						#power-domain-cells = <0>;
>  					};
> -
> -					port at 1 {
> +					pd_pu: power-domain at 1 {
>  						reg = <1>;
> -
> -						lvds0_mux_1: endpoint {
> -							remote-endpoint = <&ipu1_di1_lvds0>;
> -						};
> +						#power-domain-cells = <0>;
> +						power-supply = <&reg_pu>;
> +						clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
> +						         <&clks
> IMX6QDL_CLK_GPU3D_SHADER>,
> +						         <&clks
> IMX6QDL_CLK_GPU2D_CORE>,
> +						         <&clks IMX6QDL_CLK_GPU2D_AXI>,
> +						         <&clks
> IMX6QDL_CLK_OPENVG_AXI>,
> +						         <&clks IMX6QDL_CLK_VPU_AXI>;
>  					};
>  				};
> +			};
> 
> -				lvds-channel at 1 {
> -					#address-cells = <1>;
> -					#size-cells = <0>;
> -					reg = <1>;
> -					status = "disabled";
> -
> -					port at 0 {
> -						reg = <0>;
> -
> -						lvds1_mux_0: endpoint {
> -							remote-endpoint = <&ipu1_di0_lvds1>;
> -						};
> -					};
> +			gpr: iomuxc-gpr at 20e0000 {
> +				compatible = "fsl,imx6q-iomuxc-gpr", "syscon",
> "simple-mfd";
> +				reg = <0x20e0000 0x38>;
> 
> -					port at 1 {
> -						reg = <1>;
> -
> -						lvds1_mux_1: endpoint {
> -							remote-endpoint = <&ipu1_di1_lvds1>;
> -						};
> -					};
> +				mux: mux-controller {
> +					compatible = "mmio-mux";
> +					#mux-control-cells = <1>;
>  				};
>  			};
> 
> -			dcic1: dcic at 020e4000 {
> +			iomuxc: iomuxc at 20e0000 {
> +				compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
> +				reg = <0x20e0000 0x4000>;
> +			};
> +
> +			dcic1: dcic at 20e4000 {
>  				reg = <0x020e4000 0x4000>;
>  				interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
>  			};
> 
> -			dcic2: dcic at 020e8000 {
> +			dcic2: dcic at 20e8000 {
>  				reg = <0x020e8000 0x4000>;
>  				interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
>  			};
> 
> -			sdma: sdma at 020ec000 {
> +			sdma: sdma at 20ec000 {
>  				compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
>  				reg = <0x020ec000 0x4000>;
>  				interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
> @@ -883,7 +913,7 @@
>  			};
>  		};
> 
> -		aips-bus at 02100000 { /* AIPS2 */
> +		aips-bus at 2100000 { /* AIPS2 */
>  			compatible = "fsl,aips-bus", "simple-bus";
>  			#address-cells = <1>;
>  			#size-cells = <1>;
> @@ -892,7 +922,6 @@
> 
>  			crypto: caam at 2100000 {
>  				compatible = "fsl,sec-v4.0";
> -				fsl,sec-era = <4>;
>  				#address-cells = <1>;
>  				#size-cells = <1>;
>  				reg = <0x2100000 0x10000>;
> @@ -916,11 +945,11 @@
>  				};
>  			};
> 
> -			aipstz at 0217c000 { /* AIPSTZ2 */
> +			aipstz at 217c000 { /* AIPSTZ2 */
>  				reg = <0x0217c000 0x4000>;
>  			};
> 
> -			usbotg: usb at 02184000 {
> +			usbotg: usb at 2184000 {
>  				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
>  				reg = <0x02184000 0x200>;
>  				interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
> @@ -933,7 +962,7 @@
>  				status = "disabled";
>  			};
> 
> -			usbh1: usb at 02184200 {
> +			usbh1: usb at 2184200 {
>  				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
>  				reg = <0x02184200 0x200>;
>  				interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
> @@ -947,7 +976,7 @@
>  				status = "disabled";
>  			};
> 
> -			usbh2: usb at 02184400 {
> +			usbh2: usb at 2184400 {
>  				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
>  				reg = <0x02184400 0x200>;
>  				interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
> @@ -960,7 +989,7 @@
>  				status = "disabled";
>  			};
> 
> -			usbh3: usb at 02184600 {
> +			usbh3: usb at 2184600 {
>  				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
>  				reg = <0x02184600 0x200>;
>  				interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
> @@ -973,16 +1002,17 @@
>  				status = "disabled";
>  			};
> 
> -			usbmisc: usbmisc at 02184800 {
> +			usbmisc: usbmisc at 2184800 {
>  				#index-cells = <1>;
>  				compatible = "fsl,imx6q-usbmisc";
>  				reg = <0x02184800 0x200>;
>  				clocks = <&clks IMX6QDL_CLK_USBOH3>;
>  			};
> 
> -			fec: ethernet at 02188000 {
> +			fec: ethernet at 2188000 {
>  				compatible = "fsl,imx6q-fec";
>  				reg = <0x02188000 0x4000>;
> +				interrupt-names = "int0", "pps";
>  				interrupts-extended =
>  					<&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
>  					<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
> @@ -993,14 +1023,14 @@
>  				status = "disabled";
>  			};
> 
> -			mlb at 0218c000 {
> +			mlb at 218c000 {
>  				reg = <0x0218c000 0x4000>;
>  				interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
>  					     <0 117 IRQ_TYPE_LEVEL_HIGH>,
>  					     <0 126 IRQ_TYPE_LEVEL_HIGH>;
>  			};
> 
> -			usdhc1: usdhc at 02190000 {
> +			usdhc1: usdhc at 2190000 {
>  				compatible = "fsl,imx6q-usdhc";
>  				reg = <0x02190000 0x4000>;
>  				interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1012,7 +1042,7 @@
>  				status = "disabled";
>  			};
> 
> -			usdhc2: usdhc at 02194000 {
> +			usdhc2: usdhc at 2194000 {
>  				compatible = "fsl,imx6q-usdhc";
>  				reg = <0x02194000 0x4000>;
>  				interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1024,7 +1054,7 @@
>  				status = "disabled";
>  			};
> 
> -			usdhc3: usdhc at 02198000 {
> +			usdhc3: usdhc at 2198000 {
>  				compatible = "fsl,imx6q-usdhc";
>  				reg = <0x02198000 0x4000>;
>  				interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1036,7 +1066,7 @@
>  				status = "disabled";
>  			};
> 
> -			usdhc4: usdhc at 0219c000 {
> +			usdhc4: usdhc at 219c000 {
>  				compatible = "fsl,imx6q-usdhc";
>  				reg = <0x0219c000 0x4000>;
>  				interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1048,7 +1078,7 @@
>  				status = "disabled";
>  			};
> 
> -			i2c1: i2c at 021a0000 {
> +			i2c1: i2c at 21a0000 {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
>  				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
> @@ -1058,7 +1088,7 @@
>  				status = "disabled";
>  			};
> 
> -			i2c2: i2c at 021a4000 {
> +			i2c2: i2c at 21a4000 {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
>  				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
> @@ -1068,7 +1098,7 @@
>  				status = "disabled";
>  			};
> 
> -			i2c3: i2c at 021a8000 {
> +			i2c3: i2c at 21a8000 {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
>  				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
> @@ -1078,55 +1108,66 @@
>  				status = "disabled";
>  			};
> 
> -			romcp at 021ac000 {
> +			romcp at 21ac000 {
>  				reg = <0x021ac000 0x4000>;
>  			};
> 
> -			mmdc0: mmdc at 021b0000 { /* MMDC0 */
> +			mmdc0: mmdc at 21b0000 { /* MMDC0 */
>  				compatible = "fsl,imx6q-mmdc";
>  				reg = <0x021b0000 0x4000>;
>  			};
> 
> -			mmdc1: mmdc at 021b4000 { /* MMDC1 */
> +			mmdc1: mmdc at 21b4000 { /* MMDC1 */
>  				reg = <0x021b4000 0x4000>;
>  			};
> 
> -			weim: weim at 021b8000 {
> +			weim: weim at 21b8000 {
> +				#address-cells = <2>;
> +				#size-cells = <1>;
>  				compatible = "fsl,imx6q-weim";
>  				reg = <0x021b8000 0x4000>;
>  				interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
>  				clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
> +				fsl,weim-cs-gpr = <&gpr>;
> +				status = "disabled";
>  			};
> 
> -			ocotp: ocotp at 021bc000 {
> +			ocotp: ocotp at 21bc000 {
>  				compatible = "fsl,imx6q-ocotp", "syscon";
>  				reg = <0x021bc000 0x4000>;
>  				clocks = <&clks IMX6QDL_CLK_IIM>;
>  			};
> 
> -			tzasc at 021d0000 { /* TZASC1 */
> +			tzasc at 21d0000 { /* TZASC1 */
>  				reg = <0x021d0000 0x4000>;
>  				interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
>  			};
> 
> -			tzasc at 021d4000 { /* TZASC2 */
> +			tzasc at 21d4000 { /* TZASC2 */
>  				reg = <0x021d4000 0x4000>;
>  				interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
>  			};
> 
> -			audmux: audmux at 021d8000 {
> +			audmux: audmux at 21d8000 {
>  				compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
>  				reg = <0x021d8000 0x4000>;
>  				status = "disabled";
>  			};
> 
> -			mipi_csi: mipi at 021dc000 {
> +			mipi_csi: mipi at 21dc000 {
> +				compatible = "fsl,imx6-mipi-csi2";
>  				reg = <0x021dc000 0x4000>;
> -			};
> -
> -			mipi_dsi: mipi at 021e0000 {
>  				#address-cells = <1>;
>  				#size-cells = <0>;
> +				interrupts = <0 100 0x04>, <0 101 0x04>;
> +				clocks = <&clks IMX6QDL_CLK_HSI_TX>,
> +					 <&clks IMX6QDL_CLK_VIDEO_27M>,
> +					 <&clks IMX6QDL_CLK_EIM_PODF>;
> +				clock-names = "dphy", "ref", "pix";
> +				status = "disabled";
> +			};
> +
> +			mipi_dsi: mipi at 21e0000 {
>  				reg = <0x021e0000 0x4000>;
>  				status = "disabled";
> 
> @@ -1152,12 +1193,14 @@
>  				};
>  			};
> 
> -			vdoa at 021e4000 {
> +			vdoa at 21e4000 {
> +				compatible = "fsl,imx6q-vdoa";
>  				reg = <0x021e4000 0x4000>;
>  				interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clks IMX6QDL_CLK_VDOA>;
>  			};
> 
> -			uart2: serial at 021e8000 {
> +			uart2: serial at 21e8000 {
>  				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>  				reg = <0x021e8000 0x4000>;
>  				interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1169,7 +1212,7 @@
>  				status = "disabled";
>  			};
> 
> -			uart3: serial at 021ec000 {
> +			uart3: serial at 21ec000 {
>  				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>  				reg = <0x021ec000 0x4000>;
>  				interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1181,7 +1224,7 @@
>  				status = "disabled";
>  			};
> 
> -			uart4: serial at 021f0000 {
> +			uart4: serial at 21f0000 {
>  				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>  				reg = <0x021f0000 0x4000>;
>  				interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1193,7 +1236,7 @@
>  				status = "disabled";
>  			};
> 
> -			uart5: serial at 021f4000 {
> +			uart5: serial at 21f4000 {
>  				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>  				reg = <0x021f4000 0x4000>;
>  				interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1206,7 +1249,7 @@
>  			};
>  		};
> 
> -		ipu1: ipu at 02400000 {
> +		ipu1: ipu at 2400000 {
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			compatible = "fsl,imx6q-ipu";
> @@ -1221,6 +1264,10 @@
> 
>  			ipu1_csi0: port at 0 {
>  				reg = <0>;
> +
> +				ipu1_csi0_from_ipu1_csi0_mux: endpoint {
> +					remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
> +				};
>  			};
> 
>  			ipu1_csi1: port at 1 {
> @@ -1232,22 +1279,27 @@
>  				#size-cells = <0>;
>  				reg = <2>;
> 
> -				ipu1_di0_disp0: disp0-endpoint {
> +				ipu1_di0_disp0: endpoint at 0 {
> +					reg = <0>;
>  				};
> 
> -				ipu1_di0_hdmi: hdmi-endpoint {
> +				ipu1_di0_hdmi: endpoint at 1 {
> +					reg = <1>;
>  					remote-endpoint = <&hdmi_mux_0>;
>  				};
> 
> -				ipu1_di0_mipi: mipi-endpoint {
> +				ipu1_di0_mipi: endpoint at 2 {
> +					reg = <2>;
>  					remote-endpoint = <&mipi_mux_0>;
>  				};
> 
> -				ipu1_di0_lvds0: lvds0-endpoint {
> +				ipu1_di0_lvds0: endpoint at 3 {
> +					reg = <3>;
>  					remote-endpoint = <&lvds0_mux_0>;
>  				};
> 
> -				ipu1_di0_lvds1: lvds1-endpoint {
> +				ipu1_di0_lvds1: endpoint at 4 {
> +					reg = <4>;
>  					remote-endpoint = <&lvds1_mux_0>;
>  				};
>  			};
> @@ -1257,22 +1309,27 @@
>  				#size-cells = <0>;
>  				reg = <3>;
> 
> -				ipu1_di1_disp1: disp1-endpoint {
> +				ipu1_di1_disp1: endpoint at 0 {
> +					reg = <0>;
>  				};
> 
> -				ipu1_di1_hdmi: hdmi-endpoint {
> +				ipu1_di1_hdmi: endpoint at 1 {
> +					reg = <1>;
>  					remote-endpoint = <&hdmi_mux_1>;
>  				};
> 
> -				ipu1_di1_mipi: mipi-endpoint {
> +				ipu1_di1_mipi: endpoint at 2 {
> +					reg = <2>;
>  					remote-endpoint = <&mipi_mux_1>;
>  				};
> 
> -				ipu1_di1_lvds0: lvds0-endpoint {
> +				ipu1_di1_lvds0: endpoint at 3 {
> +					reg = <3>;
>  					remote-endpoint = <&lvds0_mux_1>;
>  				};
> 
> -				ipu1_di1_lvds1: lvds1-endpoint {
> +				ipu1_di1_lvds1: endpoint at 4 {
> +					reg = <4>;
>  					remote-endpoint = <&lvds1_mux_1>;
>  				};
>  			};
> diff --git a/arch/arm/dts/imx6qp-sabreauto.dts
> b/arch/arm/dts/imx6qp-sabreauto.dts
> new file mode 100644
> index 0000000..d4caeeb
> --- /dev/null
> +++ b/arch/arm/dts/imx6qp-sabreauto.dts
> @@ -0,0 +1,55 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +//
> +// Copyright 2016 Freescale Semiconductor, Inc.
> +
> +/dts-v1/;
> +
> +#include "imx6qp.dtsi"
> +#include "imx6qdl-sabreauto.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX6 Quad Plus SABRE Automotive Board";
> +	compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
> +};
> +
> +&i2c2 {
> +	max7322: gpio at 68 {
> +		compatible = "maxim,max7322";
> +		reg = <0x68>;
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +	};
> +};
> +
> +&iomuxc {
> +	imx6qdl-sabreauto {
> +		pinctrl_enet: enetgrp {
> +			fsl,pins = <
> +				MX6QDL_PAD_KEY_COL1__ENET_MDIO
> 0x1b0b0
> +				MX6QDL_PAD_KEY_COL2__ENET_MDC
> 0x1b0b0
> +				MX6QDL_PAD_RGMII_TXC__RGMII_TXC
> 0x1b018
> +				MX6QDL_PAD_RGMII_TD0__RGMII_TD0
> 0x1b018
> +				MX6QDL_PAD_RGMII_TD1__RGMII_TD1
> 0x1b018
> +				MX6QDL_PAD_RGMII_TD2__RGMII_TD2
> 0x1b018
> +				MX6QDL_PAD_RGMII_TD3__RGMII_TD3
> 0x1b018
> +				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL
> 0x1b018
> +				MX6QDL_PAD_RGMII_RXC__RGMII_RXC
> 0x1b018
> +				MX6QDL_PAD_RGMII_RD0__RGMII_RD0
> 0x1b018
> +				MX6QDL_PAD_RGMII_RD1__RGMII_RD1
> 0x1b018
> +				MX6QDL_PAD_RGMII_RD2__RGMII_RD2
> 0x1b018
> +				MX6QDL_PAD_RGMII_RD3__RGMII_RD3
> 0x1b018
> +				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL
> 0x1b018
> +				MX6QDL_PAD_GPIO_16__ENET_REF_CLK
> 0x4001b0a8
> +				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
> +			>;
> +		};
> +	};
> +};
> +
> +&pcie {
> +	status = "disabled";
> +};
> +
> +&vgen3_reg {
> +	regulator-always-on;
> +};
> diff --git a/arch/arm/dts/imx6qp-sabresd.dts
> b/arch/arm/dts/imx6qp-sabresd.dts
> new file mode 100644
> index 0000000..f1b9cb1
> --- /dev/null
> +++ b/arch/arm/dts/imx6qp-sabresd.dts
> @@ -0,0 +1,55 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +//
> +// Copyright 2016 Freescale Semiconductor, Inc.
> +
> +/dts-v1/;
> +
> +#include "imx6qp.dtsi"
> +#include "imx6qdl-sabresd.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
> +	compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
> +};
> +
> +&reg_arm {
> +	vin-supply = <&sw2_reg>;
> +};
> +
> +&iomuxc {
> +	imx6qdl-sabresd {
> +		pinctrl_usdhc2: usdhc2grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
> +				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10071
> +				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
> +				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
> +				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
> +				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
> +				MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
> +				MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
> +				MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
> +				MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
> +			>;
> +		};
> +
> +		pinctrl_usdhc3: usdhc3grp {
> +			fsl,pins = <
> +				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
> +				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10071
> +				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
> +				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
> +				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
> +				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
> +				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
> +				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
> +				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
> +				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
> +			>;
> +		};
> +	};
> +};
> +
> +&pcie {
> +	status = "disabled";
> +};
> diff --git a/arch/arm/dts/imx6qp.dtsi b/arch/arm/dts/imx6qp.dtsi
> new file mode 100644
> index 0000000..5f51f8e
> --- /dev/null
> +++ b/arch/arm/dts/imx6qp.dtsi
> @@ -0,0 +1,115 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +//
> +// Copyright 2016 Freescale Semiconductor, Inc.
> +
> +#include "imx6q.dtsi"
> +
> +/ {
> +	soc {
> +		ocram2: sram at 940000 {
> +			compatible = "mmio-sram";
> +			reg = <0x00940000 0x20000>;
> +			clocks = <&clks IMX6QDL_CLK_OCRAM>;
> +		};
> +
> +		ocram3: sram at 960000 {
> +			compatible = "mmio-sram";
> +			reg = <0x00960000 0x20000>;
> +			clocks = <&clks IMX6QDL_CLK_OCRAM>;
> +		};
> +
> +		aips-bus at 2100000 {
> +			pre1: pre at 21c8000 {
> +				compatible = "fsl,imx6qp-pre";
> +				reg = <0x021c8000 0x1000>;
> +				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
> +				clocks = <&clks IMX6QDL_CLK_PRE0>;
> +				clock-names = "axi";
> +				fsl,iram = <&ocram2>;
> +			};
> +
> +			pre2: pre at 21c9000 {
> +				compatible = "fsl,imx6qp-pre";
> +				reg = <0x021c9000 0x1000>;
> +				interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
> +				clocks = <&clks IMX6QDL_CLK_PRE1>;
> +				clock-names = "axi";
> +				fsl,iram = <&ocram2>;
> +			};
> +
> +			pre3: pre at 21ca000 {
> +				compatible = "fsl,imx6qp-pre";
> +				reg = <0x021ca000 0x1000>;
> +				interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
> +				clocks = <&clks IMX6QDL_CLK_PRE2>;
> +				clock-names = "axi";
> +				fsl,iram = <&ocram3>;
> +			};
> +
> +			pre4: pre at 21cb000 {
> +				compatible = "fsl,imx6qp-pre";
> +				reg = <0x021cb000 0x1000>;
> +				interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
> +				clocks = <&clks IMX6QDL_CLK_PRE3>;
> +				clock-names = "axi";
> +				fsl,iram = <&ocram3>;
> +			};
> +
> +			prg1: prg at 21cc000 {
> +				compatible = "fsl,imx6qp-prg";
> +				reg = <0x021cc000 0x1000>;
> +				clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
> +					 <&clks IMX6QDL_CLK_PRG0_AXI>;
> +				clock-names = "ipg", "axi";
> +				fsl,pres = <&pre1>, <&pre2>, <&pre3>;
> +			};
> +
> +			prg2: prg at 21cd000 {
> +				compatible = "fsl,imx6qp-prg";
> +				reg = <0x021cd000 0x1000>;
> +				clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
> +					 <&clks IMX6QDL_CLK_PRG1_AXI>;
> +				clock-names = "ipg", "axi";
> +				fsl,pres = <&pre4>, <&pre2>, <&pre3>;
> +			};
> +		};
> +	};
> +};
> +
> +&fec {
> +	/delete-property/interrupts-extended;
> +	interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
> +		     <0 119 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&gpc {
> +	compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
> +};
> +
> +&ipu1 {
> +	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
> +	fsl,prg = <&prg1>;
> +};
> +
> +&ipu2 {
> +	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
> +	fsl,prg = <&prg2>;
> +};
> +
> +&ldb {
> +	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks
> IMX6QDL_CLK_LDB_DI1_SEL>,
> +		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks
> IMX6QDL_CLK_IPU1_DI1_SEL>,
> +		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks
> IMX6QDL_CLK_IPU2_DI1_SEL>,
> +		 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks
> IMX6QDL_CLK_LDB_DI1_PODF>;
> +	clock-names = "di0_pll", "di1_pll",
> +		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
> +		      "di0", "di1";
> +};
> +
> +&mmdc0 {
> +	compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
> +};
> +
> +&pcie {
> +	compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
> +};
> --
> 2.7.4



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