[U-Boot] imx8mq-evk: Outbound network packets lost

[Sergey Kubushyn]

On Sat, 26 Jan 2019, Chris Spencer wrote:

> On Sat, 26 Jan 2019 at 01:14, Sergey Kubushyn <ksi at koi8.net> wrote:
>> Thanks for a reply. The problem here is not with leftover descriptors -- it
>> is MDIO bus not working at all. It is either bogus speed/clock in DM mode or
>> something else that I haven't found yet. Reading all zeroes means there is
>> no communication with the PHY whatsoever, it comes from bare wire. And there
>> is no need for the PHY to be present at all for an MDIO transaction to
>> complete successfully -- PHY is a slave device with all clocks coming from
>> FEC MDIO so it WILL complete successfully even if it not connected to a PHY.
>> It is kinda like SPI that always succeeds for the master.
>
> What I found when debugging the Linux driver is that an MII interrupt
> was being delivered too early after the first MDIO read the driver
> issues, resulting in it reading back the wrong value. I was able to
> reliably stop this from happening by zeroing out ENET_MMFR immediately
> before the driver sets ENET_MSCR. If I disable networking in U-Boot
> then the problem in the Linux driver doesn't occur at all, so the only
> explanation I can come up with is that U-Boot is somehow leaving
> something in ENET_MMFR which is being unintentionally triggered when
> the Linux driver sets ENET_MSCR. You have a very good point though
> because the reads are still completing in U-Boot, even if they always
> come back zero, so I'm not really sure how there would end up being
> something left over in ENET_MMFR.

OK, I've got it working. The problem was DM FEC driver does _NOT_ do pin
muxing and FEC pins in i.MX8MQ come up as GPIOs after rest so no wonder it
can't talk to the PHY or whatever else.

I don't know yet if there is some setting that I've missed to force it to do
pin muxing but didn't find anything appropriate in reference fsl-imx8mq-evk
board configs or board source files.

Once pin muxing is done in the board file FEC comes up as expected, finds
the PHY and all network stuff works as expected.

Dedicated "regulator" and PHY reset works OK from DTB provided FEC driver is
patched for regulator (regulator_set_enable instead of regulator_autoset)
and PHY reset GPIO set "ACTIVE_LOW" in the board's DTS file (fec driver sets
it to "1" to reset then resets it to "0").

So it is either pin muxing is missing and one should do it in his board's
file or I've missed some setting that I can't find to get the DM FEC driver
to do it itself from DTS file.

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