[U-Boot] [PATCH 12/13] mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timings

[Tom Rini]

On Mon, Jan 28, 2019 at 12:15:30PM +0530, Faiz Abbas wrote:

> From: Faiz Abbas <faiz4000 at gmail.com>
> 
> The HOST_CONTROL2 register is a part of SDHC v3.00 and not just specific
> to arasan/zynq controllers. Add the same to sdhci.h.
> 
> Also create a common API to set UHS timings in HOST_CONTROL2.
> 
> Signed-off-by: Faiz Abbas <faiz4000 at gmail.com>
[snip]
> diff --git a/include/sdhci.h b/include/sdhci.h
> index 725520b0b4..1e5f249eab 100644
> --- a/include/sdhci.h
> +++ b/include/sdhci.h
> @@ -144,7 +144,23 @@
>  
>  #define SDHCI_ACMD12_ERR	0x3C
>  
> -/* 3E-3F reserved */
> +#define SDHCI_HOST_CONTROL2	0x3E
> +#define  SDHCI_CTRL_UHS_MASK	0x0007
> +#define   SDHCI_CTRL_UHS_SDR12	0x0000
> +#define   SDHCI_CTRL_UHS_SDR25	0x0001
> +#define   SDHCI_CTRL_UHS_SDR50	0x0002
> +#define   SDHCI_CTRL_UHS_SDR104	0x0003
> +#define   SDHCI_CTRL_UHS_DDR50	0x0004
> +#define   SDHCI_CTRL_HS400	0x0005 /* Non-standard */
> +#define  SDHCI_CTRL_VDD_180	0x0008
> +#define  SDHCI_CTRL_DRV_TYPE_MASK	0x0030
> +#define   SDHCI_CTRL_DRV_TYPE_B	0x0000
> +#define   SDHCI_CTRL_DRV_TYPE_A	0x0010
> +#define   SDHCI_CTRL_DRV_TYPE_C	0x0020
> +#define   SDHCI_CTRL_DRV_TYPE_D	0x0030
> +#define  SDHCI_CTRL_EXEC_TUNING	0x0040
> +#define  SDHCI_CTRL_TUNED_CLK	0x0080
> +#define  SDHCI_CTRL_PRESET_VAL_ENABLE	0x8000

The defines had consistent spacing before and now don't, why?  Or please
fix.  Thanks!

-- 
Tom
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