[U-Boot] [PATCH 00/40] x86: Add support for booting from TPL
Simon Glass
sjg at chromium.org
Wed Jan 30 03:58:55 UTC 2019
At present SPL is used on 64-bit platforms, to allow SPL to be built as
a 32-bit program and U-Boot proper to be built as 64-bit.
However it is useful to be able to use SPL on any x86 platform, where
U-Boot needs to be updated in the field. Then SPL can select which U-Boot
to run (A or B) and most of the code can be updated. Similarly, using TPL
allows both SPL and U-Boot to be updated. This is the best approach, since
it means that all of U-Boot proper as well as SPL (in particular SDRAM
init) can be updated in the field. This provides for the smallest possible
amount of read-only (non-updateable) code: just the TPL code.
This series contains a number of changes to allow x86 boards to use TPL,
SPL and U-Boot proper. As a test, it is enabled for samus with a new
chromebook_samus_tpl board.
Simon Glass (40):
binman: Don't generate an error in 'text' entry constructor
binman: Don't show image-skip message by default
binman: Add a missing comment in Entry_vblock
dm: core: Fix translate condition in ofnode_get_addr_size()
cros_ec: Use a hyphen in the uclass name
spl: Allow sandbox to build a device-tree file
RFC: binman: Allow sections to have an offset
x86: start64: Fix copyright message
x86: mp_init: Use proper error numbers
x86: Add a way to reinit the cpu
x86: dts: Add device-tree labels for rtc and reset
x86: Update a stale comment about ifdtool
x86: Support SPL and TPL
x86: Support booting with TPL
x86: Add a handoff header file
x86: broadwell: Improve SDRAM debugging output
x86: broadwell: Allow SDRAM init from SPL
x86: Move init of debug UART to cpu.c
x86: broadwell: Split CPU init
x86: Add support for starting from SPL/TPL
x86: Allow 16-bit init to be in TPL
x86: broadwell: Allow booting from SPL
x86: broadwell: Select refcode and CPU code for SPL
x86: Add common Intel code for SPL
x86: Support saving MRC data from SPL
x86: Add a simple TPL implementations
x86: mrccache: Add more debugging
x86: Add a sysreset driver for the Intel PCH
x86: Support TPL in Intel common code
x86: Don't set up MTRRs in SPL
x86: Don't generate a bootstage report in SPL
x86: Support PCI VGA ROM when TPL is used
x86: sysreset: Implement the get_last() method
x86: Add documention on the samus flashmap
x86: samus: Update device tree for SPL
x86: samus: Update device tree for verified boot
x86: Update device tree for TPL
x86: Update device tree for Chromium OS verified boot
x86: Fix device-tree indentation
x86: samus: Add a target to boot through TPL
Makefile | 1 +
arch/Kconfig | 30 +
arch/x86/Kconfig | 10 +-
arch/x86/Makefile | 16 +-
arch/x86/cpu/Makefile | 15 +-
arch/x86/cpu/broadwell/Kconfig | 1 +
arch/x86/cpu/broadwell/Makefile | 23 +-
arch/x86/cpu/broadwell/cpu.c | 676 +--------------------
arch/x86/cpu/broadwell/cpu_from_spl.c | 63 ++
arch/x86/cpu/broadwell/cpu_full.c | 694 ++++++++++++++++++++++
arch/x86/cpu/broadwell/northbridge.c | 93 +++
arch/x86/cpu/broadwell/sdram.c | 136 +----
arch/x86/cpu/i386/cpu.c | 113 ++--
arch/x86/cpu/intel_common/Makefile | 17 +-
arch/x86/cpu/intel_common/car.S | 2 +-
arch/x86/cpu/intel_common/cpu_from_spl.c | 27 +
arch/x86/cpu/mp_init.c | 10 +-
arch/x86/cpu/start64.S | 2 +-
arch/x86/cpu/start_from_spl.S | 71 +++
arch/x86/cpu/start_from_tpl.S | 50 ++
arch/x86/cpu/u-boot-spl.lds | 2 +-
arch/x86/cpu/x86_64/cpu.c | 5 +
arch/x86/dts/chromebook_samus.dts | 60 +-
arch/x86/dts/reset.dtsi | 2 +-
arch/x86/dts/rtc.dtsi | 2 +-
arch/x86/dts/u-boot.dtsi | 154 +++--
arch/x86/include/asm/handoff.h | 15 +
arch/x86/include/asm/mrccache.h | 11 +
arch/x86/include/asm/spl.h | 17 +-
arch/x86/include/asm/u-boot-x86.h | 20 +
arch/x86/lib/Makefile | 9 +-
arch/x86/lib/bootm.c | 2 +-
arch/x86/lib/init_helpers.c | 5 +-
arch/x86/lib/mrccache.c | 52 +-
arch/x86/lib/spl.c | 44 +-
arch/x86/lib/tpl.c | 118 ++++
board/google/Kconfig | 8 +
board/google/chromebook_samus/Kconfig | 14 +-
board/google/chromebook_samus/MAINTAINERS | 7 +
configs/chromebook_samus_tpl_defconfig | 80 +++
doc/README.x86 | 14 +
drivers/core/ofnode.c | 2 +-
drivers/misc/cros_ec.c | 2 +-
drivers/pci/pci_rom.c | 2 +-
drivers/sysreset/Kconfig | 9 +
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_intel_pch.c | 125 ++++
drivers/sysreset/sysreset_x86.c | 6 +
include/configs/chromebook_link.h | 3 -
include/configs/chromebook_samus.h | 3 +
include/configs/qemu-x86.h | 3 -
scripts/Makefile.spl | 24 +-
tools/binman/bsection.py | 5 +-
tools/binman/control.py | 4 +-
tools/binman/etype/section.py | 3 +-
tools/binman/etype/text.py | 4 +-
tools/binman/etype/vblock.py | 1 +
57 files changed, 1933 insertions(+), 955 deletions(-)
create mode 100644 arch/x86/cpu/broadwell/cpu_from_spl.c
create mode 100644 arch/x86/cpu/broadwell/cpu_full.c
create mode 100644 arch/x86/cpu/intel_common/cpu_from_spl.c
create mode 100644 arch/x86/cpu/start_from_spl.S
create mode 100644 arch/x86/cpu/start_from_tpl.S
create mode 100644 arch/x86/include/asm/handoff.h
create mode 100644 arch/x86/lib/tpl.c
create mode 100644 configs/chromebook_samus_tpl_defconfig
create mode 100644 drivers/sysreset/sysreset_intel_pch.c
--
2.20.1.495.gaa96b0ce6b-goog
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