[U-Boot] [PATCH v7 2/7] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK

[Marek Vasut]

On 1/31/19 3:51 PM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee at intel.com>
> 
> Add default fitImage file bundling FPGA bitstreams for Arria10.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
> ---
>  board/altera/arria10-socdk/fit_spl_fpga.its | 31 +++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
>  create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its
> 
> diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its b/board/altera/arria10-socdk/fit_spl_fpga.its
> new file mode 100644
> index 0000000..46b125c
> --- /dev/null
> +++ b/board/altera/arria10-socdk/fit_spl_fpga.its
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: GPL-2.0
> + /*
> + * Copyright (C) 2019 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +/dts-v1/;
> +
> +/ {
> +	description = "FIT image with FPGA bistream";
> +	#address-cells = <1>;
> +
> +	images {
> +		fpga-2 {

Why is fpga-2 before fpga-1 ?

> +			description = "FPGA core bitstream";
> +			data = /incbin/("../../../ghrd_10as066n2.core.rbf");
> +			type = "fpga";
> +			arch = "arm";
> +			compression = "none";
> +			load = <0x400>;
> +		};
> +
> +		fpga-1 {
> +			description = "FPGA peripheral bitstream";
> +			data = /incbin/("../../../ghrd_10as066n2.periph.rbf");
> +			type = "fpga";
> +			arch = "arm";
> +			compression = "none";
> +		};
> +	};
> +};
> 


-- 
Best regards,
Marek Vasut