[U-Boot] [BUG] Wandboard fails to boot via U-Boot bootefi, GRUB
Heinrich Schuchardt
xypron.glpk at gmx.de
Mon Jul 1 17:19:10 UTC 2019
On 7/1/19 4:02 PM, Leif Lindholm wrote:
> Hi Heinrich,
>
> On Sat, Jun 29, 2019 at 07:47:10PM +0200, Heinrich Schuchardt wrote:
>> Hello Leif,
>>
>> the Wandboard Quad rev B1 cannot be booted via U-Boot, GRUB-efi-arm.
>> GRUB loads the initial ramdisk into an area which the the mainline
>> 4.19.55 kernel simply does not accept because it thinks the minimum
>> address is 0x68000000 and not 0x10000000. Booting via bootz works
>> without problem.
>>
>> Did you see a similar problems before?
>
> Hmm...
> It's been about 5 years since I looked at this code in Linux last, so
> I may need to start with some stupid questions.
>
>> This is the memory map when it is last read from U-Boot.
>>
>> typ, phys, virt, pages, attrib
>> 00000002, 8f797000, 8f797000, 869, 8
>> 00000005, 8f796000, 8f796000, 1, 8000000000000008
>> 00000002, 8dd8c000, 8dd8c000, 1a0a, 8
>> 00000000, 8dd8b000, 8dd8b000, 1, 8
>> 00000006, 8dd8a000, 8dd8a000, 1, 8000000000000008
>> 00000000, 8dd83000, 8dd83000, 7, 8
>> 00000006, 8dd82000, 8dd82000, 1, 8000000000000008
>> 00000000, 8dd7e000, 8dd7e000, 4, 8
>> 00000001, 8dd67000, 8dd67000, 17, 8
>> 00000004, 8dd66000, 8dd66000, 1, 8
>> 00000000, 8dd64000, 8dd64000, 2, 8
>> 00000002, 8dd63000, 8dd63000, 1, 8
>> 00000006, 8dd62000, 8dd62000, 1, 8000000000000008
>> 00000002, 8dd61000, 8dd61000, 1, 8
>> 00000001, 6e60c000, 6e60c000, 1f755, 8
>> 00000002, 6e1f8000, 6e1f8000, 414, 8
>> 00000001, 6dded000, 6dded000, 40b, 8
>> 00000002, 6ddec000, 6ddec000, 1, 8
>> 00000004, 6ddeb000, 6ddeb000, 1, 8
>> 00000002, 6dde9000, 6dde9000, 2, 8
>> 00000007, 2ffff000, 2ffff000, 3ddea, 8
>> 00000002, 2e1f1000, 2e1f1000, 1e0e, 8
>
> According to this, we have an allocation of somewhat below 8MB, I
> assume this matches the size of the initrd?
Thanks a lot for taking a look at this.
31516827 bytes actually.
74715648 bytes after unzipping.
>
>> 00000007, 17f0c000, 17f0c000, 162e5, 8
>> 00000004, 17f00000, 17f00000, c, 8
>> 00000002, 17d00000, 17d00000, 200, 8
>> 00000007, 1240b000, 1240b000, 58f5, 8
>> 00000002, 12000000, 12000000, 40b, 8
>> 00000004, 10000000, 10000000, 2000, 8
>>
>> The initial ramdisk is loaded at 2e1f1000.
>>
>> The problem occurs in drivers/of/fdt.c where some memory areas including
>> the one containig the initial ramdisk are excluded. I have added some
>> extra debug lines to early_init_dt_add_memory_arch().
>
> Do you have a pointer to the device tree sources?
> If the DT is explicitly excluding regions not marked such in the UEFI
> memory map ... that would cause problems.
Please, find appended the device tree passed to U-Boot (dtb) and the
printout of the devicetree upon entering SetVirtualAddressMap.
Regards
Heinrich
>
> Best Regards,
>
> Leif
>
>> [ 0.000000] Booting Linux on physical CPU 0x0
>> [ 0.000000] Linux version 4.19.55-armmp (zfsdt at family) (gcc version
>> 8.3.0 (Debian 8.3.0-6)) #8 SMP Sat Jun 29 17:04:52 CES9
>> [ 0.000000] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7),
>> cr=10c5387d
>> [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing
>> instruction cache
>> [ 0.000000] OF: fdt: Machine model: Wandboard i.MX6 Quad Board rev B1
>> [ 0.000000] OF: fdt: base 10000000 < phys_offset 68000000
>> [ 0.000000] OF: fdt: Ignoring memory range 0x10000000 - 0x68000000
>> [ 0.000000] bootconsole [earlycon0] enabled
>> [ 0.000000] Memory policy: Data cache writealloc
>> [ 0.000000] efi: Getting EFI parameters from FDT:
>> [ 0.000000] efi: EFI v2.80 by Das U-Boot
>> [ 0.000000] efi: SMBIOS=0x8dd82000
>> [ 0.000000] OF: fdt: base 0000000010000000 + size 0000000002000000 <
>> phys_offset 0000000068000000
>> [ 0.000000] OF: fdt: Ignoring memory block 0x10000000 - 0x12000000
>> [ 0.000000] OF: fdt: base 0000000012000000 + size 000000000040b000 <
>> phys_offset 0000000068000000
>> [ 0.000000] OF: fdt: Ignoring memory block 0x12000000 - 0x1240b000
>> [ 0.000000] OF: fdt: base 000000001240b000 + size 00000000058f5000 <
>> phys_offset 0000000068000000
>> [ 0.000000] OF: fdt: Ignoring memory block 0x1240b000 - 0x17d00000
>> [ 0.000000] OF: fdt: base 0000000017d00000 + size 0000000000200000 <
>> phys_offset 0000000068000000
>> [ 0.000000] OF: fdt: Ignoring memory block 0x17d00000 - 0x17f00000
>> [ 0.000000] OF: fdt: phys_offset 0000000068000000
>> [ 0.000000] OF: fdt: base 0000000017f00000 + size 000000000000c000 <
>> phys_offset 0000000068000000
>> [ 0.000000] OF: fdt: Ignoring memory block 0x17f00000 - 0x17f0c000
>> [ 0.000000] OF: fdt: phys_offset 0000000068000000
>> [ 0.000000] OF: fdt: base 0000000017f0c000 + size 00000000162e5000 <
>> phys_offset 0000000068000000
>> [ 0.000000] OF: fdt: Ignoring memory block 0x17f0c000 - 0x2e1f1000
>> [ 0.000000] OF: fdt: phys_offset 0000000068000000
>> [ 0.000000] OF: fdt: base 000000002e1f1000 + size 0000000001e0e000 <
>> phys_offset 0000000068000000
>> [ 0.000000] OF: fdt: Ignoring memory block 0x2e1f1000 - 0x2ffff000
>> [ 0.000000] INITRD: 0x2e1f1000+0x01e0e000 is not a memory region -
>> disabling initrd
>> [ 0.000000] cma: Reserved 16 MiB at 0x8e000000
>> [ 0.000000] Unable to handle kernel paging request at virtual address
>> 6fd00000
>> [ 0.000000] pgd = (ptrval)
>> [ 0.000000] [6fd00000] *pgd=00000000
>> [ 0.000000] Internal error: Oops: 5 [#1] SMP ARM
>> [ 0.000000] Modules linked in:
>> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 4.19.55-armmp #8
>> [ 0.000000] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
>> [ 0.000000] PC is at fdt_check_header+0xc/0x80
>> [ 0.000000] LR is at __unflatten_device_tree+0x4c/0x274
>> [ 0.000000] pc : [<c0ae9d48>] lr : [<c09696dc>] psr: 200000d3
>> [ 0.000000] sp : c1201ec0 ip : c1201ed0 fp : c1201ecc
>> [ 0.000000] r10: c1316340 r9 : 00000000 r8 : c135e308
>> [ 0.000000] r7 : 00000000 r6 : 6fd00000 r5 : c1074be8 r4 : c1074be8
>> [ 0.000000] r3 : c1074be8 r2 : c135e308 r1 : 00000000 r0 : 6fd00000
>> [ 0.000000] Flags: nzCv IRQs off FIQs off Mode SVC_32 ISA ARM
>> Segment none
>> [ 0.000000] Control: 10c5387d Table: 6820404a DAC: 00000051
>> [ 0.000000] Process swapper (pid: 0, stack limit = 0x(ptrval))
>> [ 0.000000] Stack: (0xc1201ec0 to 0xc1202000)
>> [ 0.000000] 1ec0: c1201efc c1201ed0 c09696dc c0ae9d48 c1074be8
>> c1074be8 c1209900 8fffffff
>> [ 0.000000] 1ee0: 8f980000 c1349880 e7fffc80 c1316340 c1201f1c
>> c1201f00 c1076000 c096969c
>> [ 0.000000] 1f00: 00000000 c1201f10 c0358230 c1083028 c1201fa4
>> c1201f20 c1004a38 c1075fc8
>> [ 0.000000] 1f20: ffffffff 10c5387d c03bcd50 c03bc83c c0d61908
>> c0d6349c c1205dcc c1201fbc
>> [ 0.000000] 1f40: c0e340c8 fffff000 c1201fa4 c1201f58 c1022158
>> c0af8b54 c1205dcc c1205dcc
>> [ 0.000000] 1f60: c1205dcc ffffffff c1201f94 c1201f78 c03bd0c8
>> 00000000 c1201f9c 00000000
>> [ 0.000000] 1f80: c1205dcc c1205dcc ffffffff c1205dc0 412fc09a
>> 10c5387d c1201ff4 c
>>
>> Best regards
>>
>> Heinrich
>
-------------- next part --------------
U-Boot SPL 2019.07-rc4-D001-00111-gfc0156b573 (Jun 29 2019 - 01:01:53 +0200)
Trying to boot from MMC1
U-Boot 2019.07-rc4-00114-g229925f66a-dirty (Jun 29 2019 - 10:58:01 +0200)
CPU: Freescale i.MX6Q rev1.2 at 792 MHz
Reset cause: WDOG
Loading Linux 4.19.55-armmp ...
Loading initial ramdisk ...
EFI stub: Booting Linux Kernel...
EFI stub: Using DTB from configuration table
EFI stub: Exiting boot services and installing virtual address map...
System table GUI eb9d2d31-2d88-11d3-9a16-0090273fc14d
System table GUI b1b621d5-f19c-41a5-830b-d9152c69aae0
/ {
#address-cells = <0x00000001>;
#size-cells = <0x00000001>;
model = "Wandboard i.MX6 Quad Board rev B1";
compatible = "wand,imx6q-wandboard", "fsl,imx6q";
chosen {
linux,initrd-end = <0x00000000 0x2fffe68b>;
linux,initrd-start = <0x00000000 0x2e1f1000>;
bootargs = "console=ttymxc0 earlyprintk";
};
memory {
reg = <0x10000000 0x80000000>;
device_type = "memory";
};
aliases {
ethernet0 = "/soc/aips-bus at 2100000/ethernet at 2188000";
can0 = "/soc/aips-bus at 2000000/flexcan at 2090000";
can1 = "/soc/aips-bus at 2000000/flexcan at 2094000";
gpio0 = "/soc/aips-bus at 2000000/gpio at 209c000";
gpio1 = "/soc/aips-bus at 2000000/gpio at 20a0000";
gpio2 = "/soc/aips-bus at 2000000/gpio at 20a4000";
gpio3 = "/soc/aips-bus at 2000000/gpio at 20a8000";
gpio4 = "/soc/aips-bus at 2000000/gpio at 20ac000";
gpio5 = "/soc/aips-bus at 2000000/gpio at 20b0000";
gpio6 = "/soc/aips-bus at 2000000/gpio at 20b4000";
i2c0 = "/soc/aips-bus at 2100000/i2c at 21a0000";
i2c1 = "/soc/aips-bus at 2100000/i2c at 21a4000";
i2c2 = "/soc/aips-bus at 2100000/i2c at 21a8000";
ipu0 = "/soc/ipu at 2400000";
mmc0 = "/soc/aips-bus at 2100000/usdhc at 2190000";
mmc1 = "/soc/aips-bus at 2100000/usdhc at 2194000";
mmc2 = "/soc/aips-bus at 2100000/usdhc at 2198000";
mmc3 = "/soc/aips-bus at 2100000/usdhc at 219c000";
serial0 = "/soc/aips-bus at 2000000/spba-bus at 2000000/serial at 2020000";
serial1 = "/soc/aips-bus at 2100000/serial at 21e8000";
serial2 = "/soc/aips-bus at 2100000/serial at 21ec000";
serial3 = "/soc/aips-bus at 2100000/serial at 21f0000";
serial4 = "/soc/aips-bus at 2100000/serial at 21f4000";
spi0 = "/soc/aips-bus at 2000000/spba-bus at 2000000/ecspi at 2008000";
spi1 = "/soc/aips-bus at 2000000/spba-bus at 2000000/ecspi at 200c000";
spi2 = "/soc/aips-bus at 2000000/spba-bus at 2000000/ecspi at 2010000";
spi3 = "/soc/aips-bus at 2000000/spba-bus at 2000000/ecspi at 2014000";
usbphy0 = "/soc/aips-bus at 2000000/usbphy at 20c9000";
usbphy1 = "/soc/aips-bus at 2000000/usbphy at 20ca000";
ipu1 = "/soc/ipu at 2800000";
spi4 = "/soc/aips-bus at 2000000/spba-bus at 2000000/ecspi at 2018000";
};
clocks {
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
#clock-cells = <0x00000000>;
clock-frequency = <0x00008000>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
#clock-cells = <0x00000000>;
clock-frequency = <0x00000000>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0x00000000>;
clock-frequency = <0x016e3600>;
};
};
tempmon {
compatible = "fsl,imx6q-tempmon";
interrupt-parent = <0x00000001>;
interrupts = <0x00000000 0x00000031 0x00000004>;
fsl,tempmon = <0x00000002>;
fsl,tempmon-data = <0x00000003>;
clocks = <0x00000004 0x000000ac>;
};
ldb {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
gpr = <0x00000005>;
status = "disabled";
clocks = <0x00000004 0x00000021 0x00000004 0x00000022 0x00000004 0x00000027 0x00000004 0x00000028 0x00000004 ;
clock-names = "di0_pll", "di1_pll", "di0_sel", "di1_sel", "di2_sel", "di3_sel", "di0", "di1";
lvds-channel at 0 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
reg = <0x00000000>;
status = "disabled";
port at 0 {
reg = <0x00000000>;
endpoint {
remote-endpoint = <0x00000006>;
phandle = <0x00000042>;
};
};
port at 1 {
reg = <0x00000001>;
endpoint {
remote-endpoint = <0x00000007>;
phandle = <0x00000046>;
};
};
port at 2 {
reg = <0x00000002>;
endpoint {
remote-endpoint = <0x00000008>;
phandle = <0x0000004c>;
};
};
port at 3 {
reg = <0x00000003>;
endpoint {
remote-endpoint = <0x00000009>;
phandle = <0x00000050>;
};
};
};
lvds-channel at 1 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
reg = <0x00000001>;
status = "disabled";
port at 0 {
reg = <0x00000000>;
endpoint {
remote-endpoint = <0x0000000a>;
phandle = <0x00000043>;
};
};
port at 1 {
reg = <0x00000001>;
endpoint {
remote-endpoint = <0x0000000b>;
phandle = <0x00000047>;
};
};
port at 2 {
reg = <0x00000002>;
endpoint {
remote-endpoint = <0x0000000c>;
phandle = <0x0000004d>;
};
};
port at 3 {
reg = <0x00000003>;
endpoint {
remote-endpoint = <0x0000000d>;
phandle = <0x00000051>;
};
};
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <0x00000001>;
interrupts = <0x00000000 0x0000005e 0x00000004>;
};
soc {
#address-cells = <0x00000001>;
#size-cells = <0x00000001>;
compatible = "simple-bus";
interrupt-parent = <0x00000001>;
ranges;
dma-apbh at 110000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x00110000 0x00002000>;
interrupts = <0x00000000 0x0000000d 0x00000004 0x00000000 0x0000000d 0x00000004 0x00000000 0x0000000d;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <0x00000001>;
dma-channels = <0x00000004>;
clocks = <0x00000004 0x0000006a>;
phandle = <0x0000000e>;
};
gpmi-nand at 112000 {
compatible = "fsl,imx6q-gpmi-nand";
#address-cells = <0x00000001>;
#size-cells = <0x00000001>;
reg = <0x00112000 0x00002000 0x00114000 0x00002000>;
reg-names = "gpmi-nand", "bch";
interrupts = <0x00000000 0x0000000f 0x00000004>;
interrupt-names = "bch";
clocks = <0x00000004 0x00000098 0x00000004 0x00000099 0x00000004 0x00000097 0x00000004 0x00000096 0x0;
clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_bch_apb", "per1_bch";
dmas = <0x0000000e 0x00000000>;
dma-names = "rx-tx";
status = "disabled";
};
hdmi at 120000 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
reg = <0x00120000 0x00009000>;
interrupts = <0x00000000 0x00000073 0x00000004>;
gpr = <0x00000005>;
clocks = <0x00000004 0x0000007b 0x00000004 0x0000007c>;
clock-names = "iahb", "isfr";
status = "okay";
compatible = "fsl,imx6q-hdmi";
ddc-i2c-bus = <0x0000000f>;
port at 0 {
reg = <0x00000000>;
endpoint {
remote-endpoint = <0x00000010>;
phandle = <0x00000040>;
};
};
port at 1 {
reg = <0x00000001>;
endpoint {
remote-endpoint = <0x00000011>;
phandle = <0x00000044>;
};
};
port at 2 {
reg = <0x00000002>;
endpoint {
remote-endpoint = <0x00000012>;
phandle = <0x0000004a>;
};
};
port at 3 {
reg = <0x00000003>;
endpoint {
remote-endpoint = <0x00000013>;
phandle = <0x0000004e>;
};
};
};
gpu at 130000 { compatible = "vivante,gc";
reg = <0x00130000 0x00004000>;
interrupts = <0x00000000 0x00000009 0x00000004>;
clocks = <0x00000004 0x0000001b 0x00000004 0x0000007a 0x00000004 0x0000004a>;
clock-names = "bus", "core", "shader";
power-domains = <0x00000014>;
};
gpu at 134000 {
compatible = "vivante,gc";
reg = <0x00134000 0x00004000>;
interrupts = <0x00000000 0x0000000a 0x00000004>;
clocks = <0x00000004 0x0000001a 0x00000004 0x00000079>;
clock-names = "bus", "core";
power-domains = <0x00000014>;
};
timer at a00600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x00a00600 0x00000020>;
interrupts = <0x00000001 0x0000000d 0x00000f01>;
interrupt-parent = <0x00000015>;
clocks = <0x00000004 0x0000000f>;
};
interrupt-controller at a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x00000003>;
interrupt-controller;
reg = <0x00a01000 0x00001000 0x00a00100 0x00000100>;
interrupt-parent = <0x00000015>;
phandle = <0x00000015>;
};
l2-cache at a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x00001000>;
interrupts = <0x00000000 0x0000005c 0x00000004>;
cache-unified;
cache-level = <0x00000002>;
arm,tag-latency = <0x00000004 0x00000002 0x00000003>;
arm,data-latency = <0x00000004 0x00000002 0x00000003>;
arm,shared-override;
phandle = <0x00000052>;
};
pcie at 1ffc000 {
compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
reg = <0x01ffc000 0x00004000 0x01f00000 0x00080000>;
reg-names = "dbi", "config";
#address-cells = <0x00000003>;
#size-cells = <0x00000002>;
device_type = "pci";
bus-range = <0x00000000 0x000000ff>;
ranges = <0x81000000 0x00000000 0x00000000 0x01f80000 0x00000000 0x00010000 0x82000000 0x00000000 0x0;
num-lanes = <0x00000001>;
interrupts = <0x00000000 0x00000078 0x00000004>;
interrupt-names = "msi";
#interrupt-cells = <0x00000001>;
interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
interrupt-map = * 0x6e1f97a0 [0x00000080];
clocks = <0x00000004 0x00000090 0x00000004 0x000000ce 0x00000004 0x000000bd>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
status = "disabled";
};
aips-bus at 2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <0x00000001>;
#size-cells = <0x00000001>;
reg = <0x02000000 0x00100000>;
ranges;
spba-bus at 2000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <0x00000001>;
#size-cells = <0x00000001>;
reg = <0x02000000 0x00040000>;
ranges;
spdif at 2004000 {
compatible = "fsl,imx35-spdif";
reg = <0x02004000 0x00004000>;
interrupts = <0x00000000 0x00000034 0x00000004>;
dmas = <0x00000016 0x0000000e 0x00000012 0x00000000 0x00000016 0x0000000f 0x00000012 ;
dma-names = "rx", "tx";
clocks = * 0x6e1f9a24 [0x00000050];
clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", "rxtx5", "rxtx6", ;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x00000017>;
phandle = <0x0000005f>;
};
ecspi at 2008000 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02008000 0x00004000>;
interrupts = <0x00000000 0x0000001f 0x00000004>;
clocks = <0x00000004 0x00000070 0x00000004 0x00000070>;
clock-names = "ipg", "per";
dmas = <0x00000016 0x00000003 0x00000008 0x00000001 0x00000016 0x00000004 0x00000008 ;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi at 200c000 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x0200c000 0x00004000>;
interrupts = <0x00000000 0x00000020 0x00000004>;
clocks = <0x00000004 0x00000071 0x00000004 0x00000071>;
clock-names = "ipg", "per";
dmas = <0x00000016 0x00000005 0x00000008 0x00000001 0x00000016 0x00000006 0x00000008 ;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi at 2010000 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02010000 0x00004000>;
interrupts = <0x00000000 0x00000021 0x00000004>;
clocks = <0x00000004 0x00000072 0x00000004 0x00000072>;
clock-names = "ipg", "per";
dmas = <0x00000016 0x00000007 0x00000008 0x00000001 0x00000016 0x00000008 0x00000008 ;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi at 2014000 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02014000 0x00004000>;
interrupts = <0x00000000 0x00000022 0x00000004>;
clocks = <0x00000004 0x00000073 0x00000004 0x00000073>;
clock-names = "ipg", "per";
dmas = <0x00000016 0x00000009 0x00000008 0x00000001 0x00000016 0x0000000a 0x00000008 ;
dma-names = "rx", "tx";
status = "disabled";
};
serial at 2020000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x00004000>;
interrupts = <0x00000000 0x0000001a 0x00000004>;
clocks = <0x00000004 0x000000a0 0x00000004 0x000000a1>;
clock-names = "ipg", "per";
dmas = <0x00000016 0x00000019 0x00000004 0x00000000 0x00000016 0x0000001a 0x00000004 ;
dma-names = "rx", "tx";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x00000018>;
};
esai at 2024000 {
#sound-dai-cells = <0x00000000>;
compatible = "fsl,imx35-esai";
reg = <0x02024000 0x00004000>;
interrupts = <0x00000000 0x00000033 0x00000004>;
clocks = <0x00000004 0x000000d0 0x00000004 0x000000d1 0x00000004 0x00000076 0x0000000;
clock-names = "core", "mem", "extal", "fsys", "spba";
dmas = <0x00000016 0x00000017 0x00000015 0x00000000 0x00000016 0x00000018 0x00000015 ;
dma-names = "rx", "tx";
status = "disabled";
};
ssi at 2028000 {
#sound-dai-cells = <0x00000000>;
compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi";
reg = <0x02028000 0x00004000>;
interrupts = <0x00000000 0x0000002e 0x00000004>;
clocks = <0x00000004 0x000000b2 0x00000004 0x0000009d>;
clock-names = "ipg", "baud";
dmas = <0x00000016 0x00000025 0x00000001 0x00000000 0x00000016 0x00000026 0x00000001 ;
dma-names = "rx", "tx";
fsl,fifo-depth = <0x0000000f>;
status = "okay";
phandle = <0x0000005d>;
};
ssi at 202c000 {
#sound-dai-cells = <0x00000000>;
compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi";
reg = <0x0202c000 0x00004000>;
interrupts = <0x00000000 0x0000002f 0x00000004>;
clocks = <0x00000004 0x000000b3 0x00000004 0x0000009e>;
clock-names = "ipg", "baud";
dmas = <0x00000016 0x00000029 0x00000001 0x00000000 0x00000016 0x0000002a 0x00000001 ;
dma-names = "rx", "tx";
fsl,fifo-depth = <0x0000000f>;
status = "disabled";
};
ssi at 2030000 {
#sound-dai-cells = <0x00000000>;
compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi";
reg = <0x02030000 0x00004000>;
interrupts = <0x00000000 0x00000030 0x00000004>;
clocks = <0x00000004 0x000000b4 0x00000004 0x0000009f>;
clock-names = "ipg", "baud";
dmas = <0x00000016 0x0000002d 0x00000001 0x00000000 0x00000016 0x0000002e 0x00000001 ;
dma-names = "rx", "tx";
fsl,fifo-depth = <0x0000000f>;
status = "disabled";
};
asrc at 2034000 {
compatible = "fsl,imx53-asrc";
reg = <0x02034000 0x00004000>;
interrupts = <0x00000000 0x00000032 0x00000004>;
clocks = * 0x6e1fa554 [0x00000098];
clock-names = "mem", "ipg", "asrck_0", "asrck_1", "asrck_2", "asrck_3", "asrck_4", "a;
dmas = * 0x6e1fa694 [0x00000060];
dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
fsl,asrc-rate = <0x0000bb80>;
fsl,asrc-width = <0x00000010>;
status = "okay";
};
spba at 203c000 {
reg = <0x0203c000 0x00004000>;
};
ecspi at 2018000 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02018000 0x00004000>;
interrupts = <0x00000000 0x00000023 0x00000004>;
clocks = <0x00000004 0x00000074 0x00000004 0x00000074>;
clock-names = "ipg", "per";
dmas = <0x00000016 0x0000000b 0x00000008 0x00000001 0x00000016 0x0000000c 0x00000008 ;
dma-names = "rx", "tx";
status = "disabled";
};
};
vpu at 2040000 {
compatible = "fsl,imx6q-vpu", "cnm,coda960";
reg = <0x02040000 0x0003c000>;
interrupts = <0x00000000 0x0000000c 0x00000004 0x00000000 0x00000003 0x00000004>;
interrupt-names = "bit", "jpeg";
clocks = <0x00000004 0x000000a8 0x00000004 0x0000008c>;
clock-names = "per", "ahb";
power-domains = <0x00000014>;
resets = <0x00000019 0x00000001>;
iram = <0x0000001a>;
};
aipstz at 207c000 {
reg = <0x0207c000 0x00004000>;
};
pwm at 2080000 {
#pwm-cells = <0x00000002>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x00004000>;
interrupts = <0x00000000 0x00000053 0x00000004>;
clocks = <0x00000004 0x0000003e 0x00000004 0x00000091>;
clock-names = "ipg", "per";
status = "disabled";
};
pwm at 2084000 {
#pwm-cells = <0x00000002>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x00004000>;
interrupts = <0x00000000 0x00000054 0x00000004>;
clocks = <0x00000004 0x0000003e 0x00000004 0x00000092>;
clock-names = "ipg", "per";
status = "disabled";
};
pwm at 2088000 {
#pwm-cells = <0x00000002>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x00004000>;
interrupts = <0x00000000 0x00000055 0x00000004>;
clocks = <0x00000004 0x0000003e 0x00000004 0x00000093>;
clock-names = "ipg", "per";
status = "disabled";
};
pwm at 208c000 {
#pwm-cells = <0x00000002>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x00004000>;
interrupts = <0x00000000 0x00000056 0x00000004>;
clocks = <0x00000004 0x0000003e 0x00000004 0x00000094>;
clock-names = "ipg", "per";
status = "disabled";
};
flexcan at 2090000 {
compatible = "fsl,imx6q-flexcan";
reg = <0x02090000 0x00004000>;
interrupts = <0x00000000 0x0000006e 0x00000004>;
clocks = <0x00000004 0x0000006c 0x00000004 0x0000006d>;
clock-names = "ipg", "per";
status = "disabled";
};
flexcan at 2094000 {
compatible = "fsl,imx6q-flexcan";
reg = <0x02094000 0x00004000>;
interrupts = <0x00000000 0x0000006f 0x00000004>;
clocks = <0x00000004 0x0000006e 0x00000004 0x0000006f>;
clock-names = "ipg", "per";
status = "disabled";
};
gpt at 2098000 {
compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
reg = <0x02098000 0x00004000>;
interrupts = <0x00000000 0x00000037 0x00000004>;
clocks = <0x00000004 0x00000077 0x00000004 0x00000078 0x00000004 0x000000ed>;
clock-names = "ipg", "per", "osc_per";
};
gpio at 209c000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x0209c000 0x00004000>;
interrupts = <0x00000000 0x00000042 0x00000004 0x00000000 0x00000043 0x00000004>;
gpio-controller;
#gpio-cells = <0x00000002>;
interrupt-controller;
#interrupt-cells = <0x00000002>;
gpio-ranges = * 0x6e1faf70 [0x00000100];
phandle = <0x00000029>;
};
gpio at 20a0000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020a0000 0x00004000>;
interrupts = <0x00000000 0x00000044 0x00000004 0x00000000 0x00000045 0x00000004>;
gpio-controller;
#gpio-cells = <0x00000002>;
interrupt-controller;
#interrupt-cells = <0x00000002>;
gpio-ranges = <0x0000001b 0x00000000 0x000000bf 0x00000010 0x0000001b 0x00000010 0x00000037 0;
};
gpio at 20a4000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020a4000 0x00004000>;
interrupts = <0x00000000 0x00000046 0x00000004 0x00000000 0x00000047 0x00000004>;
gpio-controller;
#gpio-cells = <0x00000002>;
interrupt-controller;
#interrupt-cells = <0x00000002>;
gpio-ranges = <0x0000001b 0x00000000 0x00000045 0x00000010 0x0000001b 0x00000010 0x00000024 0;
phandle = <0x0000002b>;
};
gpio at 20a8000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020a8000 0x00004000>;
interrupts = <0x00000000 0x00000048 0x00000004 0x00000000 0x00000049 0x00000004>;
gpio-controller;
#gpio-cells = <0x00000002>;
interrupt-controller;
#interrupt-cells = <0x00000002>;
gpio-ranges = <0x0000001b 0x00000005 0x00000095 0x00000001 0x0000001b 0x00000006 0x0000007e 0;
};
gpio at 20ac000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020ac000 0x00004000>;
interrupts = <0x00000000 0x0000004a 0x00000004 0x00000000 0x0000004b 0x00000004>;
gpio-controller;
#gpio-cells = <0x00000002>;
interrupt-controller;
#interrupt-cells = <0x00000002>;
gpio-ranges = * 0x6e1fb430 [0x00000050];
};
gpio at 20b0000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020b0000 0x00004000>;
interrupts = <0x00000000 0x0000004c 0x00000004 0x00000000 0x0000004d 0x00000004>;
gpio-controller;
#gpio-cells = <0x00000002>;
interrupt-controller;
#interrupt-cells = <0x00000002>;
gpio-ranges = * 0x6e1fb540 [0x00000070];
};
gpio at 20b4000 {
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
reg = <0x020b4000 0x00004000>;
interrupts = <0x00000000 0x0000004e 0x00000004 0x00000000 0x0000004f 0x00000004>;
gpio-controller;
#gpio-cells = <0x00000002>;
interrupt-controller;
#interrupt-cells = <0x00000002>;
gpio-ranges = <0x0000001b 0x00000000 0x000000ac 0x00000009 0x0000001b 0x00000009 0x000000bd 0;
};
kpp at 20b8000 {
compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x00004000>;
interrupts = <0x00000000 0x00000052 0x00000004>;
clocks = <0x00000004 0x0000003e>;
status = "disabled";
};
wdog at 20bc000 {
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x00004000>;
interrupts = <0x00000000 0x00000050 0x00000004>;
clocks = <0x00000004 0x00000000>;
5";
anatop-max-voltage = <0x0014fb18>;
anatop-enable-bit = <0x00000000>;
};
regulator-3p0 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <0x002ab980>;
regulator-max-microvolt = <0x003010b0>;
regulator-always-on;
anatop-reg-offset = <0x00000120>;
anatop-vol-bit-shift = <0x00000008>;
anatop-vol-bit-width = <0x00000005>;
anatop-min-bit-val = <0x00000000>;
anatop-min-voltage = <0x00280de8>;
anatop-max-voltage = <0x0033e140>;
anatop-enable-bit = <0x00000000>;
};
regulator-2p5 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <0x00225510>;
regulator-max-microvolt = <0x0029f630>;
regulator-always-on;
anatop-reg-offset = <0x00000130>;
anatop-vol-bit-shift = <0x00000008>;
anatop-vol-bit-width = <0x00000005>;
anatop-min-bit-val = <0x00000000>;
anatop-min-voltage = <0x00200b20>;
anatop-max-voltage = <0x002bde78>;
anatop-enable-bit = <0x00000000>;
};
regulator-vddcore {
compatible = "fsl,anatop-regulator";
regulator-name = "vddarm";
regulator-min-microvolt = <0x000b1008>;
regulator-max-microvolt = <0x00162010>;
regulator-always-on;
anatop-reg-offset = <0x00000140>;
anatop-vol-bit-shift = <0x00000000>;
anatop-vol-bit-width = <0x00000005>;
anatop-delay-reg-offset = <0x00000170>;
anatop-delay-bit-shift = <0x00000018>;
anatop-delay-bit-width = <0x00000002>;
anatop-min-bit-val = <0x00000001>;
anatop-min-voltage = <0x000b1008>;
anatop-max-voltage = <0x00162010>;
phandle = <0x00000053>;
};
regulator-vddpu {
compatible = "fsl,anatop-regulator";
regulator-name = "vddpu";
regulator-min-microvolt = <0x000b1008>;
regulator-max-microvolt = <0x00162010>;
regulator-enable-ramp-delay = <0x00000096>;
anatop-reg-offset = <0x00000140>;
anatop-vol-bit-shift = <0x00000009>;
anatop-vol-bit-width = <0x00000005>;
anatop-delay-reg-offset = <0x00000170>;
anatop-delay-bit-shift = <0x0000001a>;
anatop-delay-bit-width = <0x00000002>;
anatop-min-bit-val = <0x00000001>;
anatop-min-voltage = <0x000b1008>;
anatop-max-voltage = <0x00162010>;
phandle = <0x0000001d>;
};
regulator-vddsoc {
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <0x000b1008>;
regulator-max-microvolt = <0x00162010>;
regulator-always-on;
anatop-reg-offset = <0x00000140>;
anatop-vol-bit-shift = <0x00000012>;
anatop-vol-bit-width = <0x00000005>;
anatop-delay-reg-offset = <0x00000170>;
anatop-delay-bit-shift = <0x0000001c>;
anatop-delay-bit-width = <0x00000002>;
anatop-min-bit-val = <0x00000001>;
anatop-min-voltage = <0x000b1008>;
anatop-max-voltage = <0x00162010>;
phandle = <0x00000054>;
};
};
usbphy at 20c9000 {
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x00001000>;
interrupts = <0x00000000 0x0000002c 0x00000004>;
clocks = <0x00000004 0x000000b6>;
fsl,anatop = <0x00000002>;
phandle = <0x00000024>;
};
usbphy at 20ca000 {
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
reg = <0x020ca000 0x00001000>;
interrupts = <0x00000000 0x0000002d 0x00000004>;
clocks = <0x00000004 0x000000b7>;
fsl,anatop = <0x00000002>;
phandle = <0x00000028>;
};
snvs at 20cc000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x020cc000 0x00004000>;
phandle = <0x0000001c>;
snvs-rtc-lp {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap = <0x0000001c>;
offset = <0x00000034>;
interrupts = <0x00000000 0x00000013 0x00000004 0x00000000 0x00000014 0x00000004>;
};
snvs-poweroff {
compatible = "syscon-poweroff";
regmap = <0x0000001c>;
offset = <0x00000038>;
value = <0x00000060>;
mask = <0x00000060>;
status = "disabled";
};
snvs-lpgpr {
compatible = "fsl,imx6q-snvs-lpgpr";
};
}; epit at 20d0000 {
reg = <0x020d0000 0x00004000>;
interrupts = <0x00000000 0x00000038 0x00000004>;
};
epit at 20d4000 {
reg = <0x020d4000 0x00004000>;
interrupts = <0x00000000 0x00000039 0x00000004>;
};
src at 20d8000 {
compatible = "fsl,imx6q-src", "fsl,imx51-src";
reg = <0x020d8000 0x00004000>;
interrupts = <0x00000000 0x0000005b 0x00000004 0x00000000 0x00000060 0x00000004>;
#reset-cells = <0x00000001>;
phandle = <0x00000019>;
};
gpc at 20dc000 {
compatible = "fsl,imx6q-gpc";
reg = <0x020dc000 0x00004000>;
interrupt-controller;
#interrupt-cells = <0x00000003>;
interrupts = <0x00000000 0x00000059 0x00000004 0x00000000 0x0000005a 0x00000004>;
interrupt-parent = <0x00000015>;
clocks = <0x00000004 0x0000003e>;
clock-names = "ipg";
phandle = <0x00000001>;
pgc {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
power-domain at 0 {
reg = <0x00000000>;
#power-domain-cells = <0x00000000>;
};
power-domain at 1 {
reg = <0x00000001>;
#power-domain-cells = <0x00000000>;
power-supply = <0x0000001d>;
clocks = <0x00000004 0x0000007a 0x00000004 0x0000004a 0x00000004 0x00000079 0;
phandle = <0x00000014>;
};
};
};
iomuxc-gpr at 20e0000 {
compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
reg = <0x020e0000 0x00000038>;
phandle = <0x00000005>;
mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <0x00000001>;
mux-reg-masks = <0x00000004 0x00080000 0x00000004 0x00100000 0x0000000c 0x0000000c 0x;
phandle = <0x0000001e>;
};
ipu1_csi0_mux {
compatible = "video-mux";
mux-controls = <0x0000001e 0x00000000>;
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
port at 0 {
reg = <0x00000000>;
endpoint {
remote-endpoint = <0x0000001f>;
phandle = <0x00000035>;
};
};
port at 1 {
reg = <0x00000001>;
endpoint {
};
};
port at 2 {
reg = <0x00000002>;
endpoint {
remote-endpoint = <0x00000020>;
phandle = <0x0000003e>;
};
};
};
ipu2_csi1_mux {
compatible = "video-mux";
mux-controls = <0x0000001e 0x00000001>;
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
port at 0 {
reg = <0x00000000>;
endpoint {
remote-endpoint = <0x00000021>;
phandle = <0x00000038>;
};
};
port at 1 {
reg = <0x00000001>;
endpoint {
};
};
port at 2 {
reg = <0x00000002>;
endpoint {
remote-endpoint = <0x00000022>;
phandle = <0x00000049>;
};
};
};
};
iomuxc at 20e0000 {
compatible = "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x00004000>;
pinctrl-names = "default";
pinctrl-0 = <0x00000023>;
phandle = <0x0000001b>;
imx6qdl-wandboard {
audmuxgrp {
fsl,pins = * 0x6e1fc9a8 [0x00000060];
phandle = <0x00000034>;
};
enetgrp {
fsl,pins = * 0x6e1fca34 [0x00000198];
phandle = <0x0000002a>;
};
i2c1grp {
fsl,pins = <0x000000a4 0x000003b8 0x00000898 0x00000006 0x00000000 0x4001b8b1;
phandle = <0x0000002f>;
};
i2c2grp {
fsl,pins = <0x00000210 0x000005e0 0x000008a0 0x00000004 0x00000001 0x4001b8b1;
phandle = <0x00000030>;
};
mclkgrp {
fsl,pins = <0x00000220 0x000005f0 0x00000000 0x00000000 0x00000000 0x000130b0;
phandle = <0x00000031>;
};
spdifgrp {
fsl,pins = <0x000001e4 0x000004f8 0x00000000 0x00000003 0x00000000 0x0001b0b0;
phandle = <0x00000017>;
};
uart1grp {
fsl,pins = <0x00000280 0x00000650 0x00000000 0x00000003 0x00000000 0x0001b0b1;
phandle = <0x00000018>;
};
uart3grp {
fsl,pins = * 0x6e1fcda0 [0x00000060];
phandle = <0x0000003d>;
};
usbotggrp {
fsl,pins = <0x00000224 0x000005f4 0x00000004 0x00000003 0xff0d0101 0x00017059;
phandle = <0x00000027>;
};
usbotgvbusgrp {
fsl,pins = <0x000000a8 0x000003bc 0x00000000 0x00000005 0x00000000 0x000130b0;
phandle = <0x00000060>;
};
usdhc1grp {
fsl,pins = * 0x6e1fcec4 [0x00000090];
phandle = <0x0000002c>;
};
usdhc2grp {
fsl,pins = * 0x6e1fcf84 [0x00000090];
phandle = <0x0000002d>;
};
usdhc3grp {
fsl,pins = * 0x6e1fd044 [0x00000090];
phandle = <0x0000002e>;
};
hoggrp {
fsl,pins = * 0x6e1fd100 [0x00000108];
phandle = <0x00000023>;
};
};
};
dcic at 20e4000 {
reg = <0x020e4000 0x00004000>;
interrupts = <0x00000000 0x0000007c 0x00000004>;
};
dcic at 20e8000 {
reg = <0x020e8000 0x00004000>;
interrupts = <0x00000000 0x0000007d 0x00000004>;
};
sdma at 20ec000 {
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
reg = <0x020ec000 0x00004000>;
interrupts = <0x00000000 0x00000002 0x00000004>;
clocks = <0x00000004 0x0000003e 0x00000004 0x0000009b>;
clock-names = "ipg", "ahb";
#dma-cells = <0x00000003>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
phandle = <0x00000016>;
};
};
aips-bus at 2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <0x00000001>;
#size-cells = <0x00000001>;
reg = <0x02100000 0x00100000>;
ranges;
caam at 2100000 {
compatible = "fsl,sec-v4.0";
#address-cells = <0x00000001>;
#size-cells = <0x00000001>;
reg = <0x02100000 0x00010000>;
ranges = <0x00000000 0x02100000 0x00010000>;
clocks = <0x00000004 0x000000f1 0x00000004 0x000000f2 0x00000004 0x000000f3 0x00000004 0x0000;
clock-names = "mem", "aclk", "ipg", "emi_slow";
jr0 at 1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x00001000 0x00001000>;
interrupts = <0x00000000 0x00000069 0x00000004>;
};
jr1 at 2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x00002000 0x00001000>;
interrupts = <0x00000000 0x0000006a 0x00000004>;
};
};
aipstz at 217c000 {
reg = <0x0217c000 0x00004000>;
};
usb at 2184000 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184000 0x00000200>;
interrupts = <0x00000000 0x0000002b 0x00000004>;
clocks = <0x00000004 0x000000a2>;
fsl,usbphy = <0x00000024>;
fsl,usbmisc = <0x00000025 0x00000000>;
ahb-burst-config = <0x00000000>;
tx-burst-size-dword = <0x00000010>;
rx-burst-size-dword = <0x00000010>;
status = "okay";
vbus-supply = <0x00000026>;
pinctrl-names = "default";
pinctrl-0 = <0x00000027>;
disable-over-current;
dr_mode = "otg";
};
usb at 2184200 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184200 0x00000200>;
interrupts = <0x00000000 0x00000028 0x00000004>;
clocks = <0x00000004 0x000000a2>;
fsl,usbphy = <0x00000028>;
fsl,usbmisc = <0x00000025 0x00000001>;
dr_mode = "host";
ahb-burst-config = <0x00000000>;
tx-burst-size-dword = <0x00000010>;
rx-burst-size-dword = <0x00000010>;
status = "okay";
};
usb at 2184400 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184400 0x00000200>;
interrupts = <0x00000000 0x00000029 0x00000004>;
clocks = <0x00000004 0x000000a2>;
fsl,usbmisc = <0x00000025 0x00000002>;
dr_mode = "host";
ahb-burst-config = <0x00000000>;
tx-burst-size-dword = <0x00000010>;
rx-burst-size-dword = <0x00000010>;
status = "disabled";
};
usb at 2184600 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184600 0x00000200>;
interrupts = <0x00000000 0x0000002a 0x00000004>;
clocks = <0x00000004 0x000000a2>;
fsl,usbmisc = <0x00000025 0x00000003>;
dr_mode = "host";
ahb-burst-config = <0x00000000>;
tx-burst-size-dword = <0x00000010>;
rx-burst-size-dword = <0x00000010>;
status = "disabled";
};
usbmisc at 2184800 {
#index-cells = <0x00000001>;
compatible = "fsl,imx6q-usbmisc";
reg = <0x02184800 0x00000200>;
clocks = <0x00000004 0x000000a2>;
phandle = <0x00000025>;
};
ethernet at 2188000 {
local-mac-address = [00 1f 7b b4 03 99];
compatible = "fsl,imx6q-fec";
reg = <0x02188000 0x00004000>;
interrupt-names = "int0", "pps";
interrupts-extended = <0x00000029 0x00000006 0x00000004 0x00000015 0x00000000 0x00000077 0x00;
clocks = <0x00000004 0x00000075 0x00000004 0x00000075 0x00000004 0x000000be>;
clock-names = "ipg", "ahb", "ptp";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x0000002a>;
phy-mode = "rgmii";
phy-reset-gpios = <0x0000002b 0x0000001d 0x00000001>;
fsl,err006687-workaround-present;
};
mlb at 218c000 {
reg = <0x0218c000 0x00004000>;
interrupts = <0x00000000 0x00000035 0x00000004 0x00000000 0x00000075 0x00000004 0x00000000 0x;
};
usdhc at 2190000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02190000 0x00004000>;
interrupts = <0x00000000 0x00000016 0x00000004>;
clocks = <0x00000004 0x000000a3 0x00000004 0x000000a3 0x00000004 0x000000a3>;
clock-names = "ipg", "ahb", "per";
bus-width = <0x00000004>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x0000002c>;
cd-gpios = <0x00000029 0x00000002 0x00000001>;
};
usdhc at 2194000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02194000 0x00004000>;
interrupts = <0x00000000 0x00000017 0x00000004>;
clocks = <0x00000004 0x000000a4 0x00000004 0x000000a4 0x00000004 0x000000a4>;
clock-names = "ipg", "ahb", "per";
bus-width = <0x00000004>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x0000002d>;
non-removable;
};
usdhc at 2198000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02198000 0x00004000>;
interrupts = <0x00000000 0x00000018 0x00000004>;
clocks = <0x00000004 0x000000a5 0x00000004 0x000000a5 0x00000004 0x000000a5>;
clock-names = "ipg", "ahb", "per";
bus-width = <0x00000004>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x0000002e>;
cd-gpios = <0x0000002b 0x00000009 0x00000001>;
};
usdhc at 219c000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x0219c000 0x00004000>;
interrupts = <0x00000000 0x00000019 0x00000004>;
clocks = <0x00000004 0x000000a6 0x00000004 0x000000a6 0x00000004 0x000000a6>;
clock-names = "ipg", "ahb", "per";
bus-width = <0x00000004>;
status = "disabled";
};
i2c at 21a0000 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
reg = <0x021a0000 0x00004000>;
interrupts = <0x00000000 0x00000024 0x00000004>;
clocks = <0x00000004 0x0000007d>;
status = "okay";
clock-frequency = <0x000186a0>;
pinctrl-names = "default";
pinctrl-0 = <0x0000002f>;
phandle = <0x0000000f>;
};
i2c at 21a4000 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
reg = <0x021a4000 0x00004000>;
interrupts = <0x00000000 0x00000025 0x00000004>;
clocks = <0x00000004 0x0000007e>;
status = "okay";
clock-frequency = <0x000186a0>;
pinctrl-names = "default";
pinctrl-0 = <0x00000030>;
sgtl5000 at a {
pinctrl-names = "default";
pinctrl-0 = <0x00000031>;
compatible = "fsl,sgtl5000";
reg = <0x0000000a>;
clocks = <0x00000004 0x000000c9>;
VDDA-supply = <0x00000032>;
VDDIO-supply = <0x00000033>;
lrclk-strength = <0x00000003>;
phandle = <0x0000005e>;
};
};
i2c at 21a8000 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
reg = <0x021a8000 0x00004000>;
interrupts = <0x00000000 0x00000026 0x00000004>;
clocks = <0x00000004 0x0000007f>;
status = "disabled";
};
romcp at 21ac000 {
reg = <0x021ac000 0x00004000>;
};
mmdc at 21b0000 {
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x00004000>;
};
mmdc at 21b4000 {
reg = <0x021b4000 0x00004000>;
};
weim at 21b8000 {
#address-cells = <0x00000002>;
#size-cells = <0x00000001>;
compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x00004000>;
interrupts = <0x00000000 0x0000000e 0x00000004>;
clocks = <0x00000004 0x000000c4>;
fsl,weim-cs-gpr = <0x00000005>;
status = "disabled";
};
ocotp at 21bc000 {
compatible = "fsl,imx6q-ocotp", "syscon";
reg = <0x021bc000 0x00004000>;
clocks = <0x00000004 0x00000080>;
phandle = <0x00000003>;
};
tzasc at 21d0000 {
reg = <0x021d0000 0x00004000>;
interrupts = <0x00000000 0x0000006c 0x00000004>;
};
tzasc at 21d4000 {
reg = <0x021d4000 0x00004000>;
interrupts = <0x00000000 0x0000006d 0x00000004>;
};
audmux at 21d8000 {
compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
reg = <0x021d8000 0x00004000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x00000034>;
};
mipi at 21dc000 {
compatible = "fsl,imx6-mipi-csi2";
reg = <0x021dc000 0x00004000>;
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
interrupts = <0x00000000 0x00000064 0x00000004 0x00000000 0x00000065 0x00000004>;
clocks = <0x00000004 0x0000008a 0x00000004 0x000000ee 0x00000004 0x00000061>;
clock-names = "dphy", "ref", "pix";
status = "disabled";
port at 1 {
reg = <0x00000001>;
endpoint {
remote-endpoint = <0x00000035>;
phandle = <0x0000001f>;
};
};
port at 2 {
reg = <0x00000002>;
endpoint {
remote-endpoint = <0x00000036>;
phandle = <0x0000003f>;
};
};
port at 3 {
reg = <0x00000003>;
endpoint {
remote-endpoint = <0x00000037>;
phandle = <0x00000048>;
};
};
port at 4 {
reg = <0x00000004>;
endpoint {
remote-endpoint = <0x00000038>;
phandle = <0x00000021>;
};
};
};
mipi at 21e0000 {
reg = <0x021e0000 0x00004000>;
status = "disabled";
ports {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
port at 0 {
reg = <0x00000000>;
endpoint {
remote-endpoint = <0x00000039>;
phandle = <0x00000041>;
};
};
port at 1 {
reg = <0x00000001>;
endpoint {
remote-endpoint = <0x0000003a>;
phandle = <0x00000045>;
};
};
port at 2 {
reg = <0x00000002>;
endpoint {
remote-endpoint = <0x0000003b>;
phandle = <0x0000004b>;
};
};
port at 3 {
reg = <0x00000003>;
endpoint {
remote-endpoint = <0x0000003c>;
phandle = <0x0000004f>;
};
};
};
};
vdoa at 21e4000 { compatible = "fsl,imx6q-vdoa";
reg = <0x021e4000 0x00004000>;
interrupts = <0x00000000 0x00000012 0x00000004>;
clocks = <0x00000004 0x000000ca>;
};
serial at 21e8000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021e8000 0x00004000>;
interrupts = <0x00000000 0x0000001b 0x00000004>;
clocks = <0x00000004 0x000000a0 0x00000004 0x000000a1>;
clock-names = "ipg", "per";
dmas = <0x00000016 0x0000001b 0x00000004 0x00000000 0x00000016 0x0000001c 0x00000004 0x000000;
dma-names = "rx", "tx";
status = "disabled";
};
serial at 21ec000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021ec000 0x00004000>;
interrupts = <0x00000000 0x0000001c 0x00000004>;
clocks = <0x00000004 0x000000a0 0x00000004 0x000000a1>;
clock-names = "ipg", "per";
dmas = <0x00000016 0x0000001d 0x00000004 0x00000000 0x00000016 0x0000001e 0x00000004 0x000000;
dma-names = "rx", "tx";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x0000003d>;
uart-has-rtscts;
};
serial at 21f0000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f0000 0x00004000>;
interrupts = <0x00000000 0x0000001d 0x00000004>;
clocks = <0x00000004 0x000000a0 0x00000004 0x000000a1>;
clock-names = "ipg", "per";
dmas = <0x00000016 0x0000001f 0x00000004 0x00000000 0x00000016 0x00000020 0x00000004 0x000000;
dma-names = "rx", "tx";
status = "disabled";
};
serial at 21f4000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f4000 0x00004000>;
interrupts = <0x00000000 0x0000001e 0x00000004>;
clocks = <0x00000004 0x000000a0 0x00000004 0x000000a1>;
clock-names = "ipg", "per";
dmas = <0x00000016 0x00000021 0x00000004 0x00000000 0x00000016 0x00000022 0x00000004 0x000000;
dma-names = "rx", "tx";
status = "disabled";
};
};
ipu at 2400000 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "fsl,imx6q-ipu";
reg = <0x02400000 0x00400000>;
interrupts = <0x00000000 0x00000006 0x00000004 0x00000000 0x00000005 0x00000004>;
clocks = <0x00000004 0x00000082 0x00000004 0x00000083 0x00000004 0x00000084>;
clock-names = "bus", "di0", "di1";
resets = <0x00000019 0x00000002>;
port at 0 {
reg = <0x00000000>;
phandle = <0x00000055>;
endpoint {
remote-endpoint = <0x0000003e>;
phandle = <0x00000020>;
};
};
port at 1 {
reg = <0x00000001>;
phandle = <0x00000056>;
endpoint {
remote-endpoint = <0x0000003f>;
phandle = <0x00000036>;
};
};
port at 2 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
reg = <0x00000002>;
phandle = <0x00000059>;
endpoint at 0 {
reg = <0x00000000>;
};
endpoint at 1 {
reg = <0x00000001>;
remote-endpoint = <0x00000040>;
phandle = <0x00000010>;
};
endpoint at 2 {
reg = <0x00000002>;
remote-endpoint = <0x00000041>;
phandle = <0x00000039>;
};
endpoint at 3 {
reg = <0x00000003>;
remote-endpoint = <0x00000042>;
phandle = <0x00000006>;
};
endpoint at 4 {
reg = <0x00000004>;
remote-endpoint = <0x00000043>;
phandle = <0x0000000a>;
};
};
port at 3 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
reg = <0x00000003>;
phandle = <0x0000005a>;
endpoint at 0 {
reg = <0x00000000>;
};
endpoint at 1 {
reg = <0x00000001>;
remote-endpoint = <0x00000044>;
phandle = <0x00000011>;
};
endpoint at 2 {
reg = <0x00000002>;
remote-endpoint = <0x00000045>;
phandle = <0x0000003a>;
};
endpoint at 3 {
reg = <0x00000003>;
remote-endpoint = <0x00000046>;
phandle = <0x00000007>;
};
endpoint at 4 {
reg = <0x00000004>;
remote-endpoint = <0x00000047>;
phandle = <0x0000000b>;
};
};
};
sram at 900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x00040000>;
clocks = <0x00000004 0x0000008e>;
phandle = <0x0000001a>;
};
sata at 2200000 {
compatible = "fsl,imx6q-ahci";
reg = <0x02200000 0x00004000>;
interrupts = <0x00000000 0x00000027 0x00000004>;
clocks = <0x00000004 0x0000009a 0x00000004 0x000000bb 0x00000004 0x00000069>;
clock-names = "sata", "sata_ref", "ahb";
status = "okay";
};
gpu at 2204000 {
compatible = "vivante,gc";
reg = <0x02204000 0x00004000>;
interrupts = <0x00000000 0x0000000b 0x00000004>;
clocks = <0x00000004 0x0000008f 0x00000004 0x00000079>;
clock-names = "bus", "core";
power-domains = <0x00000014>;
};
ipu at 2800000 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "fsl,imx6q-ipu";
reg = <0x02800000 0x00400000>;
interrupts = <0x00000000 0x00000008 0x00000004 0x00000000 0x00000007 0x00000004>;
clocks = <0x00000004 0x00000085 0x00000004 0x00000086 0x00000004 0x00000089>;
clock-names = "bus", "di0", "di1";
resets = <0x00000019 0x00000004>;
port at 0 {
reg = <0x00000000>;
phandle = <0x00000057>;
endpoint {
remote-endpoint = <0x00000048>;
phandle = <0x00000037>;
};
};
port at 1 {
reg = <0x00000001>;
phandle = <0x00000058>;
endpoint {
remote-endpoint = <0x00000049>;
phandle = <0x00000022>;
};
};
port at 2 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
reg = <0x00000002>;
phandle = <0x0000005b>;
endpoint at 0 {
reg = <0x00000000>;
};
endpoint at 1 {
reg = <0x00000001>;
remote-endpoint = <0x0000004a>;
phandle = <0x00000012>;
};
endpoint at 2 {
reg = <0x00000002>;
remote-endpoint = <0x0000004b>;
phandle = <0x0000003b>;
};
endpoint at 3 {
reg = <0x00000003>;
remote-endpoint = <0x0000004c>;
phandle = <0x00000008>;
};
endpoint at 4 {
reg = <0x00000004>;
remote-endpoint = <0x0000004d>;
phandle = <0x0000000c>;
};
};
port at 3 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
reg = <0x00000003>;
phandle = <0x0000005c>;
endpoint at 1 {
reg = <0x00000001>;
remote-endpoint = <0x0000004e>;
phandle = <0x00000013>;
};
endpoint at 2 {
reg = <0x00000002>;
remote-endpoint = <0x0000004f>;
phandle = <0x0000003c>;
};
endpoint at 3 {
reg = <0x00000003>;
remote-endpoint = <0x00000050>;
phandle = <0x00000009>;
};
endpoint at 4 {
reg = <0x00000004>;
remote-endpoint = <0x00000051>;
phandle = <0x0000000d>;
};
};
};
};
cpus {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
cpu at 0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x00000000>;
next-level-cache = <0x00000052>;
operating-points = <0x00124f80 0x00137478 0x000f32a0 0x001312d0 0x000d0020 0x001312d0 0x000c15c0 0x00;
fsl,soc-operating-points = <0x00124f80 0x00137478 0x000f32a0 0x001312d0 0x000d0020 0x001312d0 0x000c1;
clock-latency = <0x0000ee6c>;
#cooling-cells = <0x00000002>;
clocks = <0x00000004 0x00000068 0x00000004 0x00000006 0x00000004 0x00000010 0x00000004 0x00000011 0x0;
clock-names = "arm", "pll2_pfd2_396m", "step", "pll1_sw", "pll1_sys";
arm-supply = <0x00000053>;
pu-supply = <0x0000001d>;
soc-supply = <0x00000054>;
};
cpu at 1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x00000001>;
next-level-cache = <0x00000052>;
operating-points = <0x00124f80 0x00137478 0x000f32a0 0x001312d0 0x000d0020 0x001312d0 0x000c15c0 0x00;
fsl,soc-operating-points = <0x00124f80 0x00137478 0x000f32a0 0x001312d0 0x000d0020 0x001312d0 0x000c1;
clock-latency = <0x0000ee6c>;
clocks = <0x00000004 0x00000068 0x00000004 0x00000006 0x00000004 0x00000010 0x00000004 0x00000011 0x0;
clock-names = "arm", "pll2_pfd2_396m", "step", "pll1_sw", "pll1_sys";
arm-supply = <0x00000053>;
pu-supply = <0x0000001d>;
soc-supply = <0x00000054>;
};
cpu at 2 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x00000002>;
next-level-cache = <0x00000052>;
operating-points = <0x00124f80 0x00137478 0x000f32a0 0x001312d0 0x000d0020 0x001312d0 0x000c15c0 0x00;
fsl,soc-operating-points = <0x00124f80 0x00137478 0x000f32a0 0x001312d0 0x000d0020 0x001312d0 0x000c1;
clock-latency = <0x0000ee6c>;
clocks = <0x00000004 0x00000068 0x00000004 0x00000006 0x00000004 0x00000010 0x00000004 0x00000011 0x0;
clock-names = "arm", "pll2_pfd2_396m", "step", "pll1_sw", "pll1_sys";
arm-supply = <0x00000053>;
pu-supply = <0x0000001d>;
soc-supply = <0x00000054>;
};
cpu at 3 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x00000003>;
next-level-cache = <0x00000052>;
operating-points = <0x00124f80 0x00137478 0x000f32a0 0x001312d0 0x000d0020 0x001312d0 0x000c15c0 0x00;
fsl,soc-operating-points = <0x00124f80 0x00137478 0x000f32a0 0x001312d0 0x000d0020 0x001312d0 0x000c1;
clock-latency = <0x0000ee6c>;
clocks = <0x00000004 0x00000068 0x00000004 0x00000006 0x00000004 0x00000010 0x00000004 0x00000011 0x0;
clock-names = "arm", "pll2_pfd2_396m", "step", "pll1_sw", "pll1_sys";
arm-supply = <0x00000053>;
pu-supply = <0x0000001d>;
soc-supply = <0x00000054>;
};
};
capture-subsystem {
compatible = "fsl,imx-capture-subsystem";
ports = <0x00000055 0x00000056 0x00000057 0x00000058>;
};
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <0x00000059 0x0000005a 0x0000005b 0x0000005c>;
};
sound {
compatible = "fsl,imx6-wandboard-sgtl5000", "fsl,imx-audio-sgtl5000";
model = "imx6-wandboard-sgtl5000";
ssi-controller = <0x0000005d>;
audio-codec = <0x0000005e>;
audio-routing = "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", "Headphone Jack", "HP_OUT";
mux-int-port = <0x00000001>;
mux-ext-port = <0x00000003>;
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <0x0000005f>;
spdif-out;
};
regulator-2p5v {
compatible = "regulator-fixed";
regulator-name = "2P5V";
regulator-min-microvolt = <0x002625a0>;
regulator-max-microvolt = <0x002625a0>;
regulator-always-on;
phandle = <0x00000032>;
};
regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <0x00325aa0>;
regulator-max-microvolt = <0x00325aa0>;
regulator-always-on;
phandle = <0x00000033>;
};
regulator-usbotgvbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <0x004c4b40>;
regulator-max-microvolt = <0x004c4b40>;
pinctrl-names = "default";
pinctrl-0 = <0x00000060>;
gpio = <0x0000002b 0x00000016 0x00000001>;
phandle = <0x00000026>;
};
memory at 10000000 {
reg = <0x10000000 0x80000000>;
};
};
System table GUI e03fc20a-85dc-406e-b90e-4ab502371d95
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.19.55-armmp (zfsdt at family) (gcc version 8.3.0 (Debian 8.3.0-6)) #2 SMP Sun Jun 23 16:43:54 CES9
[ 0.000000] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] OF: fdt: Machine model: Wandboard i.MX6 Quad Board rev B1
[ 0.000000] OF: fdt: Ignoring memory range 0x10000000 - 0x41000000
[ 0.000000] bootconsole [earlycon0] enabled
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: EFI v2.80 by Das U-Boot
[ 0.000000] efi: SMBIOS=0x8dd82000
[ 0.000000] OF: fdt: Ignoring memory block 0x10000000 - 0x12000000
[ 0.000000] OF: fdt: Ignoring memory block 0x12000000 - 0x1240b000
[ 0.000000] OF: fdt: Ignoring memory block 0x1240b000 - 0x17d00000
[ 0.000000] OF: fdt: Ignoring memory block 0x17d00000 - 0x17f00000
[ 0.000000] OF: fdt: Ignoring memory block 0x17f00000 - 0x17f0c000
[ 0.000000] OF: fdt: Ignoring memory block 0x17f0c000 - 0x2e1f1000
[ 0.000000] OF: fdt: Ignoring memory block 0x2e1f1000 - 0x2ffff000
[ 0.000000] OF: fdt: Ignoring memory range 0x2ffff000 - 0x41000000
[ 0.000000] INITRD: 0x2e1f1000+0x01e0e000 is not a memory region - disabling initrd
[ 0.000000] cma: Reserved 16 MiB at 0x8e000000
[ 0.000000] BUG: not creating mapping for 0x41000000 at 0x99000000 in user region
[ 0.000000] Unable to handle kernel paging request at virtual address 0c0e1000
[ 0.000000] pgd = (ptrval)
[ 0.000000] [0c0e1000] *pgd=00000000
[ 0.000000] Internal error: Oops: 805 [#1] SMP ARM
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 4.19.55-armmp #2
[ 0.000000] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
[ 0.000000] PC is at memset+0x30/0xa8
[ 0.000000] LR is at (null)
[ 0.000000] pc : [<c0ae8530>] lr : [<00000000>] psr: 200000d3
[ 0.000000] sp : c1201db0 ip : 0c0e1000 fp : c1201df4
[ 0.000000] r10: c12ef940 r9 : 00000000 r8 : 00000000
[ 0.000000] r7 : 00041000 r6 : 00000000 r5 : 0c0e1000 r4 : 00b1c000
[ 0.000000] r3 : 00000000 r2 : 00b1bfc0 r1 : 00000000 r0 : 0c0e1000
[ 0.000000] Flags: nzCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment none
[ 0.000000] Control: 10c5387d Table: 6820404a DAC: 00000051
[ 0.000000] Process swapper (pid: 0, stack limit = 0x(ptrval))
[ 0.000000] Stack: (0xc1201db0 to 0xc1202000)
[ 0.000000] 1da0: c1201e88 c102ef2c 00000000 c03bcd2c
[ 0.000000] 1dc0: c0d8eb6c 8ffef000 00001000 00000001 00000000 00000000 00000000 c12ef940
[ 0.000000] 1de0: 00000000 00000024 c1201e1c c1201df8 c0aff6ac c102ee90 00000000 c12ef940
[ 0.000000] 1e00: c1201e74 c12ef940 c1201e7c 00000000 c1201e74 c1201e20 c1029134 c0aff63c
[ 0.000000] 1e20: 00001000 00000000 c1201e54 c1201e38 c102ec8c c050244c ffffffff 00000000
[ 0.000000] 1e40: 00001000 c124fb40 c1201e6c 00090000 c1205dcc 00041000 00090000 00000fff
[ 0.000000] 1e60: c1349880 ffe00000 c1201ebc c1201e78 c10072e4 c1029044 c1201e94 0004f000
[ 0.000000] 1e80: 00000000 00000000 00000000 00000000 00000000 00000000 c131676c e7fef000
[ 0.000000] 1ea0: 00000000 c0e34058 f4420fff c120c0c4 c1201f1c c1201ec0 c100927c c10071f0
[ 0.000000] 1ec0: 00000000 c1093000 c1205dcc c1082f34 00069200 00068300 c1201f1c ffff1000
[ 0.000000] 1ee0: 0008fff5 00001000 00000007 00000000 58000000 c1082f34 c120b1e4 693626af
[ 0.000000] 1f00: c1091e8f 68208000 0000005f c1316340 c1201fa4 c1201f20 c10047e4 c1008c9c
[ 0.000000] 1f20: 0000006c 10c5387d c03bcd50 c03bc83c c0d61908 c0d6349c c1205dcc c1201fbc
[ 0.000000] 1f40: c0e340c8 fffff000 c1201fa4 c1201f58 c1022158 c0af8b54 c1205dcc c1205dcc
[ 0.000000] 1f60: c1205dcc ffffffff c1201f94 c1201f78 c03bd0c8 00000000 c1201f9c 00000000
[ 0.000000] 1f80: c1205dcc c1205dcc ffffffff c1205dc0 412fc09a 10c5387d c1201ff4 c1201fa8
[ 0.000000] 1fa0: c1000c2c c10040f8 00000000 00000000 00000000 00000000 00000000 c1091e40
[ 0.000000] 1fc0: 00000000 00000000 00000000 c1000330 00000051 10c0387d ffffffff 17d00000
[ 0.000000] 1fe0: 412fc09a 10c5387d 00000000 c1201ff8 00000000 c1000bbc 00000000 00000000
[ 0.000000] [<c0ae8530>] (memset) from [<c102ef2c>] (memblock_virt_alloc_try_nid_nopanic+0xa8/0xb8)
[ 0.000000] [<c102ef2c>] (memblock_virt_alloc_try_nid_nopanic) from [<c0aff6ac>] (alloc_node_mem_map.constprop.10+0x7c/0xf)
[ 0.000000] [<c0aff6ac>] (alloc_node_mem_map.constprop.10) from [<c1029134>] (free_area_init_node+0xfc/0x330)
[ 0.000000] [<c1029134>] (free_area_init_node) from [<c10072e4>] (bootmem_init+0x100/0x140)
[ 0.000000] [<c10072e4>] (bootmem_init) from [<c100927c>] (paging_init+0x5ec/0x668)
[ 0.000000] [<c100927c>] (paging_init) from [<c10047e4>] (setup_arch+0x6f8/0xd88)
[ 0.000000] [<c10047e4>] (setup_arch) from [<c1000c2c>] (start_kernel+0x7c/0x504)
[ 0.000000] [<c1000c2c>] (start_kernel) from [<00000000>] ( (null))
[ 0.000000] Code: e92d4100 e1a08001 e1a0e003 e2522040 (a8ac410a)
[ 0.000000] random: get_random_bytes called from print_oops_end_marker+0x34/0x5c with crng_init=0
[ 0.000000] ---[ end trace 0000000000000000 ]---
[ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
[ 0.000000] ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]---
CTRL-A Z for help | 115200 8N1 | NOR | Minicom 2.7.1 | VT102 | Offline | ttyUSB0
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