[U-Boot] [PATCH 05/52] tools: imx8m_image: align spl bin image size

[peng.fan at nxp.com]

From: Peng Fan <peng.fan at nxp.com>

Align spl bin image size to 4 byte aligned, because we need
to pad ddr firmware in the end of spl bin. However when enable
SPL OF, the spl dtb will be padded to u-boot-nodtb.bin, then
u-boot-spl.bin size might not be 4 bytes aligned.

ddr_load_train_firmware in drivers/ddr/imx/imx8m/helper.c use 4 bytes
aligned address to load ddr firmware, so we need make sure
u-boot-spl.bin is 4 bytes aligned, in this patch we use dd
to create a new file named u-boot-spl-pad.bin, then pad ddr firmware.

If SPL OF not enabled, this patch not hurt, because `_end` already
is 4 bytes aligned.

Signed-off-by: Peng Fan <peng.fan at nxp.com>
---
 tools/imx8m_image.sh | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/tools/imx8m_image.sh b/tools/imx8m_image.sh
index ec0881a128..b4a3e204d0 100755
--- a/tools/imx8m_image.sh
+++ b/tools/imx8m_image.sh
@@ -35,8 +35,9 @@ if [ $post_process = 1 ]; then
 		objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_2d_imem.bin lpddr4_pmu_train_2d_imem_pad.bin
 		cat lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin > lpddr4_pmu_train_1d_fw.bin
 		cat lpddr4_pmu_train_2d_imem_pad.bin $srctree/lpddr4_pmu_train_2d_dmem.bin > lpddr4_pmu_train_2d_fw.bin
-		cat spl/u-boot-spl.bin lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin > spl/u-boot-spl-ddr.bin
-		rm -f lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin lpddr4_pmu_train_2d_imem_pad.bin
+		dd if=$srctree/spl/u-boot-spl.bin of=spl/u-boot-spl-pad.bin bs=4 conv=sync
+		cat spl/u-boot-spl-pad.bin lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin > spl/u-boot-spl-ddr.bin
+		rm -f lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin lpddr4_pmu_train_2d_imem_pad.bin spl/u-boot-spl-pad.bin
 	fi
 fi
 
-- 
2.16.4