[U-Boot] [PATCH v2 0/7] sunxi: Add H6 DDR3 DRAM support

[Andre Przywara]

An updated version, with minor changes.
I realised that my comments about JEDEC values were still based on the
DDR3-1600 speed bin, so I updated those to match the DDR3-1333 values.
I also used the actual JEDEC recommended formulas where that didn't
change the actual value written.
For more details see the Changelog below.
----------------

So far the SPL DRAM driver for the Allwinner H6 SoC only supports
LPDDR3 DRAM chips, which are used on most single board computers with
this SoC.
There are some TV boxes with the H6 out now, but most of them are
using DDR3 DRAM instead of LPDDR3.

This series extends the existing H6 DRAM driver to cover DDR3 DRAMs
as well. The information used in these patches is from:
- register dumps after Allwinner's boot0 (libdram) has initialised
  the DRAM
- some disassembly of the libdram library
- timing parameters as found in the boot0 binary
- comparison with Xilinx ZynqMP DRAM controller documentation

The box I played with (Eachlink H6 Mini) has 3GB of DDR3-1600 chips and
runs at 840 MHz, however I couldn't get it to work with these parameters.
Instead Jernej suggested to use a lower clock and adjust some timing
parameters, which made it work for me as well.

Many thanks to Jernej Skrabec for his help, also to others who helped
with testing and experiments.

The first two patches contain some fixes for the existing driver.
Patch 3 moves the existing LPDDR3 timing parameters into a separate file,
patch 5 introduces the respective DDR3 timings, patch 6 adds some
generic delay lines values.
Patch 4 enhances the DRAM controller driver to program DDR3 specific
registers as well and use different settings on other registers.
The final patch introduces support for the Eachlink H6 Mini TV box, with
the usual device tree and defconfig file.

Please have a look and comment!

Cheers,
Andre.

Changelog v1..v2:
- name DDR2T mode bit
- explain bonding ID bit
- generalise message about non-supported DRAM types
- update comments about JEDEC values to match DDR3-1333 timings
- use recommended max(ns, cycles) timing formulas where appropriate
- add MAINTAINERS entry for the Eachlink H6 Mini box


Andre Przywara (6):
  sunxi: H6: DRAM: avoid memcpy() on MMIO registers
  sunxi: H6: DRAM: follow recommended PHY init algorithm
  sunxi: H6: move LPDDR3 timing definition into separate file
  sunxi: H6: Add DDR3 support to DRAM controller driver
  sunxi: H6: Add DDR3-1333 timings
  sunxi: H6: Add basic Eachlink H6 Mini support

Jernej Skrabec (1):
  sunxi: H6: Add DDR3 DRAM delay values

 arch/arm/dts/Makefile                         |   1 +
 arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts   | 116 ++++++++
 .../include/asm/arch-sunxi/dram_sun50i_h6.h   |  35 +++
 arch/arm/mach-sunxi/Kconfig                   |  18 +-
 arch/arm/mach-sunxi/Makefile                  |   1 +
 arch/arm/mach-sunxi/dram_sun50i_h6.c          | 251 ++++++------------
 arch/arm/mach-sunxi/dram_timings/Makefile     |   2 +
 .../mach-sunxi/dram_timings/h6_ddr3_1333.c    | 144 ++++++++++
 .../mach-sunxi/dram_timings/h6_lpddr3_1333.c  | 132 +++++++++
 board/sunxi/MAINTAINERS                       |   6 +
 configs/eachlink_h6_mini_defconfig            |  17 ++
 configs/orangepi_one_plus_defconfig           |   1 +
 configs/pine_h64_defconfig                    |   1 +
 13 files changed, 547 insertions(+), 178 deletions(-)
 create mode 100644 arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts
 create mode 100644 arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c
 create mode 100644 arch/arm/mach-sunxi/dram_timings/h6_lpddr3_1333.c
 create mode 100644 configs/eachlink_h6_mini_defconfig

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2.17.1