[U-Boot] [RESEND PATCH v2 04/15] arm: socfpga: agilex: Add reset manager support

[Ley Foon Tan]

Add reset manager support for Agilex.

Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
---
 .../mach-socfpga/include/mach/reset_manager.h |  5 ++-
 .../include/mach/reset_manager_agilex.h       | 38 +++++++++++++++++++
 arch/arm/mach-socfpga/reset_manager.c         |  9 +++--
 3 files changed, 48 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index e2dce4b4fb..f752f7abb8 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -36,7 +36,8 @@ void socfpga_per_reset_all(void);
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)	RSTMGR_##_name
 
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+	defined(CONFIG_TARGET_SOCFPGA_AGILEX)
 
 void reset_deassert_peripherals_handoff(void);
 int cpu_has_been_warmreset(void);
@@ -68,6 +69,8 @@ void socfpga_bridges_reset(int enable);
 #include <asm/arch/reset_manager_arria10.h>
 #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
 #include <asm/arch/reset_manager_s10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+#include <asm/arch/reset_manager_agilex.h>
 #endif
 
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h
new file mode 100644
index 0000000000..c209fb439b
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef	_RESET_MANAGER_AGILEX_
+#define	_RESET_MANAGER_AGILEX_
+
+struct socfpga_reset_manager {
+	u32	status;
+	u32	mpu_rst_stat;
+	u32	misc_stat;
+	u32	padding1;
+	u32	hdsk_en;
+	u32	hdsk_req;
+	u32	hdsk_ack;
+	u32	hdsk_stall;
+	u32	mpumodrst;
+	u32	per0modrst;
+	u32	per1modrst;
+	u32	brgmodrst;
+	u32	padding2;
+	u32	cold_mod_reset;
+	u32	padding3;
+	u32	dbg_mod_reset;
+	u32	padding4;
+	u32	padding5;
+	u32	padding6;
+	u32	brg_warm_mask;
+	u32	padding7[3];
+	u32	tst_stat;
+	u32	padding8;
+	u32	hdsk_timeout;
+	u32	mpul2flushtimeout;
+	u32	dbghdsktimeout;
+};
+
+#endif /* _RESET_MANAGER_AGILEX_ */
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index e0a01ed07a..5dfe303940 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -8,13 +8,15 @@
 #include <asm/io.h>
 #include <asm/arch/reset_manager.h>
 
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+	defined(CONFIG_TARGET_SOCFPGA_AGILEX)
 #include <asm/arch/mailbox_s10.h>
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10) && \
+	!defined(CONFIG_TARGET_SOCFPGA_AGILEX)
 static const struct socfpga_reset_manager *reset_manager_base =
 		(void *)SOCFPGA_RSTMGR_ADDRESS;
 #endif
@@ -25,7 +27,8 @@ static const struct socfpga_reset_manager *reset_manager_base =
 void reset_cpu(ulong addr)
 {
 	/* request a warm reset */
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+	defined(CONFIG_TARGET_SOCFPGA_AGILEX)
 	puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
 	mbox_reset_cold();
 #else
-- 
2.19.0