[U-Boot] [PATCH v2 0/7] Support Andes RISC-V l2cache on AE350 platform

[Andes]

From: Rick Chen <rick at andestech.com>

Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse and configure the
cache settings (data & instruction prefetch, data & tag latency)
from the device tree blob.

Also implement L2 cache flush and disable before jump to linux.
The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Changes in v2:
- Add new patch [1/7] to support dm cache uclass enable and disable ops.
- Use ofdata_to_platdata() to parse and save register base instead of global data.
- Rename compatible string of "cache" as "v5l2cache".
- make v512_init() return void.
- Use dm cache uclass api to disable L2 cache.

Rick Chen (7):
  dm: cache: Add enable and disable ops for cache uclass
  dm: cache: add v5l2 cache controller driver
  riscv: ae350: use the v5l2 driver to configure the cache
  riscv: ax25: add imply v5l2 cache controller
  riscv: cache: Flush L2 cache before jump to linux
  riscv: dts: move out AE350 L2 node from cpus node
  riscv: ax25: use CCTL to flush d-cache

 arch/riscv/cpu/ax25/Kconfig             |   1 +
 arch/riscv/cpu/ax25/cache.c             |  22 +++---
 arch/riscv/cpu/ax25/cpu.c               |  26 +++++++
 arch/riscv/dts/ae350_32.dts             |  17 +++--
 arch/riscv/dts/ae350_64.dts             |  17 +++--
 arch/riscv/include/asm/v5l2cache.h      |  58 +++++++++++++++
 board/AndesTech/ax25-ae350/ax25-ae350.c |   9 +++
 drivers/cache/Kconfig                   |   9 +++
 drivers/cache/Makefile                  |   1 +
 drivers/cache/cache-uclass.c            |  20 ++++++
 drivers/cache/cache-v5l2.c              | 121 ++++++++++++++++++++++++++++++++
 include/cache.h                         |  31 ++++++++
 test/dm/cache.c                         |   2 +
 13 files changed, 313 insertions(+), 21 deletions(-)
 create mode 100644 arch/riscv/include/asm/v5l2cache.h
 create mode 100644 drivers/cache/cache-v5l2.c

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2.7.4