[U-Boot] [RESEND PATCH v2 11/15] ddr: altera: agilex: Add SDRAM driver for Agilex
Simon Goldschmidt
simon.k.r.goldschmidt at gmail.com
Tue Jul 9 20:37:55 UTC 2019
Am 04.07.2019 um 10:56 schrieb Ley Foon Tan:
> Add SDRAM driver for Agilex SoC.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
> ---
> drivers/ddr/altera/Kconfig | 6 +-
> drivers/ddr/altera/Makefile | 1 +
> drivers/ddr/altera/sdram_agilex.c | 158 ++++++++++++++++++++++++++++++
So this file contains a specialization of what you now called the
"common" driver? Please change "common" into a matching code name and
rename this file "sdram_whatever_agilex.c" so that people see this
dependency from the file name.
Regards,
Simon
> drivers/ddr/altera/sdram_common.c | 1 +
> drivers/ddr/altera/sdram_common.h | 1 +
> 5 files changed, 164 insertions(+), 3 deletions(-)
> create mode 100644 drivers/ddr/altera/sdram_agilex.c
>
> diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
> index 2b1c1be3b5..8f590dc5f6 100644
> --- a/drivers/ddr/altera/Kconfig
> +++ b/drivers/ddr/altera/Kconfig
> @@ -1,8 +1,8 @@
> config SPL_ALTERA_SDRAM
> bool "SoCFPGA DDR SDRAM driver in SPL"
> depends on SPL
> - depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10
> - select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
> - select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
> + depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
> + select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
> + select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
> help
> Enable DDR SDRAM controller for the SoCFPGA devices.
> diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
> index 09454461a9..b3b48948bf 100644
> --- a/drivers/ddr/altera/Makefile
> +++ b/drivers/ddr/altera/Makefile
> @@ -10,4 +10,5 @@ ifdef CONFIG_$(SPL_)ALTERA_SDRAM
> obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
> obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
> obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_common.o sdram_s10.o
> +obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_common.o sdram_agilex.o
> endif
> diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c
> new file mode 100644
> index 0000000000..20913ccfa7
> --- /dev/null
> +++ b/drivers/ddr/altera/sdram_agilex.c
> @@ -0,0 +1,158 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <div64.h>
> +#include <fdtdec.h>
> +#include <ram.h>
> +#include <reset.h>
> +#include "sdram_common.h"
> +#include <wait_bit.h>
> +#include <asm/arch/firewall.h>
> +#include <asm/arch/reset_manager.h>
> +#include <asm/arch/system_manager.h>
> +#include <asm/io.h>
> +#include <linux/sizes.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int sdram_mmr_init_full(struct udevice *dev)
> +{
> + struct altera_sdram_platdata *plat = dev->platdata;
> + struct altera_sdram_priv *priv = dev_get_priv(dev);
> + u32 i;
> + int ret;
> + phys_size_t hw_size;
> + bd_t bd = {0};
> +
> + /* Ensure HMC clock is running */
> + if (poll_hmc_clock_status()) {
> + debug("DDR: Error as HMC clock was not running\n");
> + return -EPERM;
> + }
> +
> + /* Trying 3 times to do a calibration */
> + for (i = 0; i < 3; i++) {
> + ret = wait_for_bit_le32((const void *)(plat->hmc +
> + DDRCALSTAT),
> + DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
> + false);
> + if (!ret)
> + break;
> +
> + emif_reset(plat);
> + }
> +
> + if (ret) {
> + puts("DDR: Error as SDRAM calibration failed\n");
> + return -EPERM;
> + }
> + debug("DDR: Calibration success\n");
> +
> + /*
> + * Configure the DDR IO size [0xFFCFB008]
> + * niosreserve0: Used to indicate DDR width &
> + * bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
> + * bit[8] = 1 if user-mode OCT is present
> + * bit[9] = 1 if warm reset compiled into EMIF Cal Code
> + * bit[10] = 1 if warm reset is on during generation in EMIF Cal
> + * niosreserve1: IP ADCDS version encoded as 16 bit value
> + * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
> + * 3=EAP, 4-6 are reserved)
> + * bit[5:3] = Service Pack # (e.g. 1)
> + * bit[9:6] = Minor Release #
> + * bit[14:10] = Major Release #
> + */
> + /* Configure DDR IO size x16, x32 and x64 mode */
> + u32 update_value;
> +
> + update_value = hmc_readl(plat, NIOSRESERVED0);
> + update_value = (update_value & 0xFF) >> 5;
> +
> + /* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */
> + update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4) >> 1;
> + hmc_ecc_writel(plat, update_value, DDRIOCTRL);
> +
> + /* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */
> + hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
> +
> + /* assigning the SDRAM size */
> + phys_size_t size = sdram_calculate_size(plat);
> +
> + if (size <= 0)
> + hw_size = PHYS_SDRAM_1_SIZE;
> + else
> + hw_size = size;
> +
> + /* Get bank configuration from devicetree */
> + ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
> + (phys_size_t *)&gd->ram_size, &bd);
> + if (ret) {
> + puts("DDR: Failed to decode memory node\n");
> + return -1;
> + }
> +
> + if (gd->ram_size != hw_size)
> + printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n");
> +
> + printf("DDR: %lld MiB\n", gd->ram_size >> 20);
> +
> + /* This enables nonsecure access to DDR */
> + /* mpuregion0addr_limit */
> + FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
> + FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
> + FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
> +
> + /* nonmpuregion0addr_limit */
> + FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
> + FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
> +
> + /* Enable mpuregion0enable and nonmpuregion0enable */
> + FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
> + FW_MPU_DDR_SCR_EN_SET);
> +
> + u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
> +
> + /* Enable or disable the DDR ECC */
> + if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
> + setbits_le32(plat->hmc + ECCCTRL1,
> + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
> + DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
> + DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
> + clrbits_le32(plat->hmc + ECCCTRL1,
> + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
> + DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
> + setbits_le32(plat->hmc + ECCCTRL2,
> + (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
> + DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
> + setbits_le32(plat->hmc + ERRINTEN,
> + DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK);
> +
> + /* Enable non-secure writes to HMC Adapter for SDRAM ECC */
> + writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
> +
> + if (!cpu_has_been_warmreset())
> + sdram_init_ecc_bits(&bd);
> + } else {
> + clrbits_le32(plat->hmc + ECCCTRL1,
> + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
> + DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
> + DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
> + clrbits_le32(plat->hmc + ECCCTRL2,
> + (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
> + DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
> + }
> +
> + sdram_size_check(&bd);
> +
> + priv->info.base = bd.bi_dram[0].start;
> + priv->info.size = gd->ram_size;
> +
> + debug("DDR: HMC init success\n");
> + return 0;
> +}
> diff --git a/drivers/ddr/altera/sdram_common.c b/drivers/ddr/altera/sdram_common.c
> index 24ab5f932b..d3a45c0ae7 100644
> --- a/drivers/ddr/altera/sdram_common.c
> +++ b/drivers/ddr/altera/sdram_common.c
> @@ -292,6 +292,7 @@ static struct ram_ops altera_sdram_ops = {
>
> static const struct udevice_id altera_sdram_ids[] = {
> { .compatible = "altr,sdr-ctl-s10" },
> + { .compatible = "altr,sdr-ctl-agilex" },
> { /* sentinel */ }
> };
>
> diff --git a/drivers/ddr/altera/sdram_common.h b/drivers/ddr/altera/sdram_common.h
> index 814ab52be3..89cea3d003 100644
> --- a/drivers/ddr/altera/sdram_common.h
> +++ b/drivers/ddr/altera/sdram_common.h
> @@ -69,6 +69,7 @@ struct altera_sdram_platdata {
> /* HMC MMR IO48 registers */
> #define CTRLCFG0 0x28
> #define CTRLCFG1 0x2c
> +#define CTRLCFG3 0x34
> #define DRAMTIMING0 0x50
> #define CALTIMING0 0x7c
> #define CALTIMING1 0x80
>
More information about the U-Boot
mailing list