[U-Boot] [RESEND PATCH v2 08/15] arm: socfpga: agilex: Add clock manager support

[Ley Foon Tan]

On Tue, Jul 9, 2019 at 1:16 PM Simon Goldschmidt
<simon.k.r.goldschmidt at gmail.com> wrote:
>
> Am 04.07.2019 um 10:56 schrieb Ley Foon Tan:
> > Add clock manager support for Agilex.
> >
> > Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
> >
> > ---
> > v2:
> > - Get clocks from clock DM.
>
> Wait, can you explain this a bit more? If you get clocks from DM, why is
> this arch-specific driver needed at all? Can't you just convert the
> callers into calling into the right clock driver directly?
>
This mainly is a wrapper to call clock DM function to get clock
frequency and print clock summary in SPL, call in
cm_print_clock_quick_summary().

Each driver like MMC driver will not  use this.

Regards
Ley Foon

>
> > ---
> >   arch/arm/mach-socfpga/Makefile                |  4 +
> >   arch/arm/mach-socfpga/clock_manager_agilex.c  | 87 +++++++++++++++++++
> >   .../include/mach/clock_manager_agilex.h       |  2 +
> >   3 files changed, 93 insertions(+)
> >   create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c
> >
> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> > index 11370cf4c4..5bb36d07df 100644
> > --- a/arch/arm/mach-socfpga/Makefile
> > +++ b/arch/arm/mach-socfpga/Makefile
> > @@ -40,6 +40,10 @@ obj-y      += wrap_pinmux_config_s10.o
> >   obj-y       += wrap_pll_config_s10.o
> >   endif
> >
> > +ifdef CONFIG_TARGET_SOCFPGA_AGILEX
> > +obj-y        += clock_manager_agilex.o
> > +endif
> > +
> >   ifdef CONFIG_SPL_BUILD
> >   ifdef CONFIG_TARGET_SOCFPGA_GEN5
> >   obj-y       += spl_gen5.o
> > diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c
> > new file mode 100644
> > index 0000000000..5159415fbf
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
> > @@ -0,0 +1,87 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2019 Intel Corporation <www.intel.com>
> > + *
> > + */
> > +
> > +#include <clk.h>
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <asm/arch/clock_manager.h>
> > +#include <asm/arch/system_manager.h>
> > +#include <asm/io.h>
> > +#include <dt-bindings/clock/stratix10-clock.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +static const struct socfpga_system_manager *sysmgr_regs =
> > +             (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > +
> > +static ulong cm_get_rate_dm(u32 id)
> > +{
> > +     struct udevice *dev;
> > +     struct clk clk;
> > +     ulong rate;
> > +     int ret;
> > +
> > +     ret = uclass_get_device_by_driver(UCLASS_CLK,
> > +                                       DM_GET_DRIVER(socfpga_agilex_clk),
> > +                                       &dev);
> > +     if (ret)
> > +             return 0;
> > +
> > +     clk.id = id;
> > +     ret = clk_request(dev, &clk);
> > +     if (ret < 0)
> > +             return 0;
> > +
> > +     rate = clk_get_rate(&clk);
> > +
> > +     clk_free(&clk);
> > +
> > +     if ((rate == (unsigned long)-ENOSYS) ||
> > +         (rate == (unsigned long)-ENXIO) ||
> > +         (rate == (unsigned long)-EIO)) {
> > +             debug("%s id %u: clk_get_rate err: %ld\n",
> > +                   __func__, id, rate);
> > +             return 0;
> > +     }
> > +
> > +     return rate;
> > +}
> > +
> > +static u32 cm_get_rate_dm_khz(u32 id)
> > +{
> > +     return cm_get_rate_dm(id) / 1000;
> > +}
> > +
> > +unsigned long cm_get_mpu_clk_hz(void)
> > +{
> > +     return cm_get_rate_dm(STRATIX10_MPU_CLK);
> > +}
> > +
> > +unsigned int cm_get_l4_sys_free_clk_hz(void)
> > +{
> > +     return cm_get_rate_dm(STRATIX10_L4_SYS_FREE_CLK);
> > +}
> > +
> > +u32 cm_get_qspi_controller_clk_hz(void)
> > +{
> > +     return readl(&sysmgr_regs->boot_scratch_cold0);
> > +}
> > +
> > +void cm_print_clock_quick_summary(void)
> > +{
> > +     printf("MPU       %10d kHz\n",
> > +            cm_get_rate_dm_khz(STRATIX10_MPU_CLK));
> > +     printf("L4 Main     %8d kHz\n",
> > +            cm_get_rate_dm_khz(STRATIX10_L4_MAIN_CLK));
> > +     printf("L4 sys free %8d kHz\n",
> > +            cm_get_rate_dm_khz(STRATIX10_L4_SYS_FREE_CLK));
> > +     printf("L4 MP       %8d kHz\n",
> > +            cm_get_rate_dm_khz(STRATIX10_L4_MP_CLK));
> > +     printf("L4 SP       %8d kHz\n",
> > +            cm_get_rate_dm_khz(STRATIX10_L4_SP_CLK));
> > +     printf("SDMMC       %8d kHz\n",
> > +            cm_get_rate_dm_khz(STRATIX10_SDMMC_CLK));
> > +}
> > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
> > index bf5e7c8775..c4d27bad72 100644
> > --- a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
> > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
> > @@ -25,6 +25,8 @@ const unsigned int cm_get_osc_clk_hz(void);
> >   const unsigned int cm_get_intosc_clk_hz(void);
> >   const unsigned int cm_get_fpga_clk_hz(void);
> >
> > +unsigned long cm_get_mpu_clk_hz(void);
> > +
> >   #define CLKMGR_EOSC1_HZ             25000000
> >   #define CLKMGR_INTOSC_HZ    400000000
> >   #define CLKMGR_FPGA_CLK_HZ  50000000
> >
>