[U-Boot] [PATCH 02/16] dts: Add initial support for bcm2838
andrei at gherzan.ro
andrei at gherzan.ro
Tue Jul 16 13:37:49 UTC 2019
From: Andrei Gherzan <andrei at gherzan.ro>
Signed-off-by: Andrei Gherzan <andrei at gherzan.ro>
---
arch/arm/dts/Makefile | 4 +-
arch/arm/dts/bcm2838-rpi-4-b.dts | 56 ++++++++
arch/arm/dts/bcm2838.dtsi | 237 +++++++++++++++++++++++++++++++
3 files changed, 296 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/bcm2838-rpi-4-b.dts
create mode 100644 arch/arm/dts/bcm2838.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 20dbc2ff84..16790af1e1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -749,7 +749,9 @@ dtb-$(CONFIG_ARCH_BCM283X) += \
bcm2837-rpi-3-a-plus.dtb \
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \
- bcm2837-rpi-cm3-io3.dtb
+ bcm2837-rpi-cm3-io3.dtb \
+ bcm2837-rpi-3-b.dtb \
+ bcm2838-rpi-4-b.dtb
dtb-$(CONFIG_ARCH_BCM63158) += \
bcm963158.dtb
diff --git a/arch/arm/dts/bcm2838-rpi-4-b.dts b/arch/arm/dts/bcm2838-rpi-4-b.dts
new file mode 100644
index 0000000000..07e9a78e8d
--- /dev/null
+++ b/arch/arm/dts/bcm2838-rpi-4-b.dts
@@ -0,0 +1,56 @@
+/dts-v1/;
+#include "bcm2838.dtsi"
+
+/ {
+ compatible = "raspberrypi,4-model-b","brcm,bcm2838","brcm,bcm2837";
+ model = "Raspberry Pi 4 Model B";
+
+ memory {
+ reg = <0 0 0x40000000>;
+ };
+
+ leds {
+ act {
+ gpios = <&gpio 47 0>;
+ };
+ };
+};
+
+/* uart0 communicates with the BT module */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>;
+ status = "okay";
+};
+
+/* uart1 is mapped to the pin header */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
+
+/* SDHCI is used to control the SDIO for wireless */
+&sdhci {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_gpio34>;
+ status = "okay";
+ bus-width = <4>;
+ non-removable;
+};
+
+/* SDHOST is used to drive the SD card */
+&sdhost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhost_gpio48>;
+ status = "okay";
+ bus-width = <4>;
+};
+
+&gpio {
+ uart1_pins: uart1_pins {
+ brcm,pins;
+ brcm,function;
+ brcm,pull;
+ };
+};
diff --git a/arch/arm/dts/bcm2838.dtsi b/arch/arm/dts/bcm2838.dtsi
new file mode 100644
index 0000000000..19b2d7b905
--- /dev/null
+++ b/arch/arm/dts/bcm2838.dtsi
@@ -0,0 +1,237 @@
+#include "bcm283x.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/raspberrypi-power.h>
+
+/ {
+ compatible = "brcm,bcm2838";
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ soc {
+ ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
+ <0x7c000000 0x0 0xfc000000 0x02000000>,
+ <0x40000000 0x0 0xff800000 0x00800000>;
+ dma-ranges = <0xc0000000 0x0 0x00000000 0x3c000000>;
+
+ gic: gic400 at 40041000 {
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ compatible = "arm,gic-400";
+ reg = <0x40041000 0x1000>,
+ <0x40042000 0x2000>,
+ <0x40044000 0x2000>,
+ <0x40046000 0x2000>;
+ };
+
+ thermal: thermal at 7d5d2200 {
+ compatible = "brcm,avs-tmon-bcm2838";
+ reg = <0x7d5d2200 0x2c>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tmon";
+ clocks = <&clocks BCM2835_CLOCK_TSENS>;
+ #thermal-sensor-cells = <0>;
+ status = "okay";
+ };
+
+ spi at 7e204000 {
+ reg = <0x7e204000 0x0200>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pixelvalve at 7e206000 {
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pixelvalve at 7e207000 {
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ hvs at 7e400000 {
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ emmc2: emmc2 at 7e340000 {
+ compatible = "brcm,bcm2711-emmc2";
+ status = "okay";
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2838_CLOCK_EMMC2>;
+ reg = <0x7e340000 0x100>;
+ };
+
+ pixelvalve at 7e807000 {
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ };
+
+ arm-pmu {
+ /*
+ * N.B. the A72 PMU support only exists in arch/arm64, hence
+ * the fallback to the A53 version.
+ */
+ compatible = "arm,cortex-a72-pmu", "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ arm,cpu-registers-not-fw-configured;
+ always-on;
+ };
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000d8>;
+ };
+
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000e0>;
+ };
+
+ cpu2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000e8>;
+ };
+
+ cpu3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000f0>;
+ };
+ };
+};
+
+&clk_osc {
+ clock-frequency = <54000000>;
+};
+
+&clocks {
+ compatible = "brcm,bcm2838-cprman";
+};
+
+&cpu_thermal {
+ coefficients = <(-487) 410040>;
+};
+
+&dsi0 {
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&dsi1 {
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio {
+ compatible = "brcm,bcm2838-gpio", "brcm,bcm2835-gpio";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&vec {
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usb {
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&hdmi {
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart1 {
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&spi1 {
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&spi2 {
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c0 {
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c1 {
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c2 {
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&mailbox {
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sdhost {
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart0 {
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&dma {
+ reg = <0x7e007000 0xb00>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 7 */
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 8 */
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 9 */
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; /* dmalite 10 */
+ interrupt-names = "dma0",
+ "dma1",
+ "dma2",
+ "dma3",
+ "dma4",
+ "dma5",
+ "dma6",
+ "dma7",
+ "dma8",
+ "dma9",
+ "dma10";
+ brcm,dma-channel-mask = <0x07f5>;
+};
--
2.22.0
More information about the U-Boot
mailing list