[U-Boot] [RFC PATCH 9/9] doc: board: Add Intel Crown Bay board doc

Wed Jul 17 05:05:05 UTC 2019

Hi Heinrich,

On Wed, Jul 17, 2019 at 2:03 AM Heinrich Schuchardt <xypron.glpk at gmx.de> wrote:
>
> On 7/16/19 6:42 PM, Bin Meng wrote:
> > This extracts Intel Crown Bay board specific information from
> > README.x86, converts plain text documentation to reST format and
> > adds it to Sphinx TOC tree. No essential content change.
> >
> > Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
> >
> > ---
> >
> >  doc/README.x86               | 37 ---------------------------------
> >  doc/board/index.rst          |  2 ++
> >  doc/board/intel/crownbay.rst | 49 ++++++++++++++++++++++++++++++++++++++++++++
> >  doc/board/intel/index.rst    |  4 ++++
> >  4 files changed, 55 insertions(+), 37 deletions(-)
> >  create mode 100644 doc/board/intel/crownbay.rst
> >  create mode 100644 doc/board/intel/index.rst
> >
> > diff --git a/doc/README.x86 b/doc/README.x86
> > index 8e0a3f3..8077ff3 100644
> > --- a/doc/README.x86
> > +++ b/doc/README.x86
> > @@ -203,43 +203,6 @@ Flash map for samus / broadwell:
> >
> >  ---
> >
> > -Intel Crown Bay specific instructions for bare mode:
> > -
> > -U-Boot support of Intel Crown Bay board [4] relies on a binary blob called
> > -Firmware Support Package [5] to perform all the necessary initialization steps
> > -as documented in the BIOS Writer Guide, including initialization of the CPU,
> > -memory controller, chipset and certain bus interfaces.
> > -
> > -Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
> > -install it on your host and locate the FSP binary blob. Note this platform
> > -also requires a Chipset Micro Code (CMC) state machine binary to be present in
> > -the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
> > -in this FSP package too.
> > -
> > -* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
> > -* ./Microcode/C0_22211.BIN
> > -
> > -Rename the first one to fsp.bin and second one to cmc.bin and put them in the
> > -board directory.
> > -
> > -Note the FSP release version 001 has a bug which could cause random endless
> > -loop during the FspInit call. This bug was published by Intel although Intel
> > -did not describe any details. We need manually apply the patch to the FSP
> > -binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
> > -binary, change the following five bytes values from orginally E8 42 FF FF FF
> > -to B8 00 80 0B 00.
> > -
> > -As for the video ROM, you need manually extract it from the Intel provided
> > -BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM
> > -ID 8086:4108, extract and save it as vga.bin in the board directory.
> > -
> > -Now you can build U-Boot and obtain u-boot.rom
> > -
> > -$ make crownbay_defconfig
> > -$ make all
> > -
> > ----
> > -
> >  Intel Cougar Canyon 2 specific instructions for bare mode:
> >
> >  This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors
> > diff --git a/doc/board/index.rst b/doc/board/index.rst
> > index 4a65def..34e59de 100644
> > --- a/doc/board/index.rst
> > +++ b/doc/board/index.rst
> > @@ -4,3 +4,5 @@ Board-specific doc
> >
> >  .. toctree::
> >     :maxdepth: 2
> > +
> > +   intel/index
> > diff --git a/doc/board/intel/crownbay.rst b/doc/board/intel/crownbay.rst
> > new file mode 100644
> > index 0000000..d77cece
> > --- /dev/null
> > +++ b/doc/board/intel/crownbay.rst
> > @@ -0,0 +1,49 @@
> > +.. SPDX-License-Identifier: GPL-2.0+
> > +
> > +:author: Bin Meng <bmeng.cn at gmail.com>
> > +
> > +.. toctree::
> > +   :maxdepth: 2
> > +
> > +Intel CrownBay CRB
> > +==================
> > +
> > +U-Boot support of Intel Crown Bay board `[1]`_ relies on a binary blob called
> > +Firmware Support Package `[2]`_ to perform all the necessary initialization
> > +steps as documented in the BIOS Writer Guide, including initialization of the
> > +CPU, memory controller, chipset and certain bus interfaces.
> > +
> > +Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
> > +install it on your host and locate the FSP binary blob. Note this platform
> > +also requires a Chipset Micro Code (CMC) state machine binary to be present in
> > +the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
> > +in this FSP package too.
> > +
> > +* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
> > +* ./Microcode/C0_22211.BIN
> > +
> > +Rename the first one to fsp.bin and second one to cmc.bin and put them in the
> > +board directory.
> > +
> > +Note the FSP release version 001 has a bug which could cause random endless
> > +loop during the FspInit call. This bug was published by Intel although Intel
> > +did not describe any details. We need manually apply the patch to the FSP
> > +binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
> > +binary, change the following five bytes values from orginally E8 42 FF FF FF
> > +to B8 00 80 0B 00.
> > +
> > +As for the video ROM, you need manually extract it from the Intel provided
> > +BIOS for Crown Bay here `[3]`_, using the AMI MMTool `[4]`_. Check PCI option
> > +ROM ID 8086:4108, extract and save it as vga.bin in the board directory.
> > +
> > +Now you can build U-Boot and obtain u-boot.rom
> > +
> > +.. code-block:: shell
> > +
> > +   $ make crownbay_defconfig
> > +   $ make all
> > +
>
> The following lines do not show up in the generated HTML. Please, recheck.
>

There are hyperlinks, so will not show up in HTML.

I will update the doc a little bit, to remove the [1]/[2]/[3]/[4].

Regards,
Bin