[U-Boot] [PATCH u-boot-spi 1/1] spi: mvebu_a3700_spi: Fix clock prescale computation

[Marek Behún]

The prescaler value computation can yield wrong result if given 0x1f at
the beginning: the value is computed to be 0x20, but the maximum value
the register can hold 0x1f, so the actual stored value in this case is
0, which is obviously wrong. The first condition should also take care
of the 0x1f value.

Signed-off-by: Marek Behún <marek.behun at nic.cz>
---
 drivers/spi/mvebu_a3700_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c
index feeafdceaa..cc73ff3fee 100644
--- a/drivers/spi/mvebu_a3700_spi.c
+++ b/drivers/spi/mvebu_a3700_spi.c
@@ -181,7 +181,7 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
 	data = readl(&reg->cfg);
 
 	prescale = DIV_ROUND_UP(clk_get_rate(&plat->clk), hz);
-	if (prescale > 0x1f)
+	if (prescale >= 0x1f)
 		prescale = 0x1f;
 	else if (prescale > 0xf)
 		prescale = 0x10 + (prescale + 1) / 2;
-- 
2.21.0