[U-Boot] [PATCH 5/5] mx7ulp_evk: Update DDR freq to 352.8Mhz for ULP B0

[sbabic at denx.de]

> From: Ye Li <ye.li at nxp.com>
> On i.MX7ULP B0, the DDR clock target is increased from 320Mhz to 380Mhz.
> We update DDR clock relevant settings to approach the target. But since the
> limitation on LCDIF pix clock for HDMI output
> (refer "mx7ulp_evk: Change APLL and its PFD0 frequencies"), we set DDR
> clock to 352.8Mhz (25.2Mhz * 14) by using the clock path:
> 	APLL PFD0 -> DDR CLK -> NIC0 -> NIC1 -> LCDIF clock
> To reduce the impact to entire system, the NIC0_DIV and NIC1_DIV are kept,
> so the divider 14 is calculated as:
> 	14 = (NIC0_DIV + 1) * (NIC1_DIV + 1) * (LCDIF_PCC_DIV + 1)
> 	NIC0_DIV:      1
> 	NIC1_DIV:      0
> 	LCDIF_PCC_DIV: 6
> APLL and APLL PFD0 settings:
> 	PFD0 FRAC:  27
> 	APLL MULT:  22
> 	APLL NUM:   1
> 	APLL DENOM: 20
> This patch applies the new settings for both DCD and plugin.
> There is no DDR script change on this new frequency.
> Overnight memtester is passed.
> Signed-off-by: Ye Li <ye.li at nxp.com>
> Reviewed-by: Peng Fan <peng.fan at nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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