[U-Boot] [PATCH 33/47] P3041: dts: Added PCIe DT nodes

[Hou Zhiqiang]

P3041 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
---
 arch/powerpc/dts/p3041.dtsi | 48 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi
index 7d5c713..197896d 100644
--- a/arch/powerpc/dts/p3041.dtsi
+++ b/arch/powerpc/dts/p3041.dtsi
@@ -60,4 +60,52 @@
 			clock-frequency = <0x0>;
 		};
 	};
+
+	pcie at ffe200000 {
+		compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe201000 {
+		compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe202000 {
+		compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe203000 {
+		compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe203000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <3>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
 };
-- 
2.9.5