[U-Boot] [PATCH v2 1/3] armv8: ls1088aqds: The ls1088aqds board supports the I2C driver model.
Chuanhua Han
chuanhua.han at nxp.com
Fri Jul 26 12:25:35 UTC 2019
This patch is updating ls1088aqds board init code to support DM_I2C.
Signed-off-by: Chuanhua Han <chuanhua.han at nxp.com>
---
depends on:
- http://patchwork.ozlabs.org/project/uboot/list/?series=110856
- http://patchwork.ozlabs.org/project/uboot/list/?series=109459
- http://patchwork.ozlabs.org/project/uboot/list/?series=120936
Changes in v2:
- Simplify i2c_write related function calls and reduce
the amount of code by using circular iteration
- Place the variable definitions for udevice at
the beginning of the function
board/freescale/ls1088a/eth_ls1088aqds.c | 149 +++++++++++++++++++++----------
include/configs/ls1088aqds.h | 4 +-
2 files changed, 104 insertions(+), 49 deletions(-)
diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c
index f16b78c..6fb671f 100644
--- a/board/freescale/ls1088a/eth_ls1088aqds.c
+++ b/board/freescale/ls1088a/eth_ls1088aqds.c
@@ -80,11 +80,16 @@ struct ls1088a_qds_mdio {
struct mii_dev *realbus;
};
+struct reg_pair {
+ uint addr;
+ u8 *val;
+};
+
static void sgmii_configure_repeater(int dpmac)
{
struct mii_dev *bus;
uint8_t a = 0xf;
- int i, j, ret;
+ int i, j, k, ret;
unsigned short value;
const char *dev = "LS1088A_QDS_MDIO2";
int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
@@ -96,8 +101,28 @@ static void sgmii_configure_repeater(int dpmac)
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+ u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
+ struct reg_pair reg_pair[10] = {
+ {6, ®_val[0]}, {4, ®_val[1]},
+ {8, ®_val[2]}, {0xf, NULL},
+ {0x11, NULL}, {0x16, NULL},
+ {0x18, NULL}, {0x23, ®_val[3]},
+ {0x2d, ®_val[4]}, {4, ®_val[5]},
+ };
+#ifdef CONFIG_DM_I2C
+ struct udevice *udev;
+#endif
+
/* Set I2c to Slot 1 */
- i2c_write(0x77, 0, 0, &a, 1);
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(0x77, 0, 0, &a, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
+ if (!ret)
+ ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+ if (ret)
+ goto error;
switch (dpmac) {
case 1:
@@ -143,31 +168,34 @@ static void sgmii_configure_repeater(int dpmac)
return;
}
+#ifdef CONFIG_DM_I2C
+ i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
+#endif
+
for (i = 0; i < 4; i++) {
for (j = 0; j < 4; j++) {
- a = 0x18;
- i2c_write(i2c_phy_addr, 6, 1, &a, 1);
- a = 0x38;
- i2c_write(i2c_phy_addr, 4, 1, &a, 1);
- a = 0x4;
- i2c_write(i2c_phy_addr, 8, 1, &a, 1);
-
- i2c_write(i2c_phy_addr, 0xf, 1,
- &ch_a_eq[i], 1);
- i2c_write(i2c_phy_addr, 0x11, 1,
- &ch_a_ctl2[j], 1);
-
- i2c_write(i2c_phy_addr, 0x16, 1,
- &ch_b_eq[i], 1);
- i2c_write(i2c_phy_addr, 0x18, 1,
- &ch_b_ctl2[j], 1);
-
- a = 0x14;
- i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
- a = 0xb5;
- i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
- a = 0x20;
- i2c_write(i2c_phy_addr, 4, 1, &a, 1);
+ reg_pair[3].val = &ch_a_eq[i];
+ reg_pair[4].val = &ch_a_ctl2[j];
+ reg_pair[5].val = &ch_b_eq[i];
+ reg_pair[6].val = &ch_b_ctl2[j];
+ for (k = 0; k < 10; k++) {
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(i2c_phy_addr,
+ reg_pair[k].addr,
+ 1, reg_pair[k].val, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0,
+ i2c_phy_addr,
+ 1, &udev);
+ if (!ret)
+ ret = dm_i2c_write(udev,
+ reg_pair[k].addr,
+ reg_pair[k].val, 1);
+#endif
+ if (ret)
+ goto error;
+ }
+
mdelay(100);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
if (ret > 0)
@@ -202,7 +230,7 @@ error:
static void qsgmii_configure_repeater(int dpmac)
{
uint8_t a = 0xf;
- int i, j;
+ int i, j, k;
int i2c_phy_addr = 0;
int phy_addr = 0;
int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
@@ -212,12 +240,32 @@ static void qsgmii_configure_repeater(int dpmac)
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+ u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
+ struct reg_pair reg_pair[10] = {
+ {6, ®_val[0]}, {4, ®_val[1]},
+ {8, ®_val[2]}, {0xf, NULL},
+ {0x11, NULL}, {0x16, NULL},
+ {0x18, NULL}, {0x23, ®_val[3]},
+ {0x2d, ®_val[4]}, {4, ®_val[5]},
+ };
+
const char *dev = mdio_names[EMI1_SLOT1];
int ret = 0;
unsigned short value;
+#ifdef CONFIG_DM_I2C
+ struct udevice *udev;
+#endif
/* Set I2c to Slot 1 */
- i2c_write(0x77, 0, 0, &a, 1);
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(0x77, 0, 0, &a, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
+ if (!ret)
+ ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+ if (ret)
+ goto error;
switch (dpmac) {
case 7:
@@ -251,28 +299,35 @@ static void qsgmii_configure_repeater(int dpmac)
return;
}
+#ifdef CONFIG_DM_I2C
+ i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
+#endif
+
for (i = 0; i < 4; i++) {
for (j = 0; j < 4; j++) {
- a = 0x18;
- i2c_write(i2c_phy_addr, 6, 1, &a, 1);
- a = 0x38;
- i2c_write(i2c_phy_addr, 4, 1, &a, 1);
- a = 0x4;
- i2c_write(i2c_phy_addr, 8, 1, &a, 1);
-
- i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
- i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
-
- i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
- i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
-
- a = 0x14;
- i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
- a = 0xb5;
- i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
- a = 0x20;
- i2c_write(i2c_phy_addr, 4, 1, &a, 1);
- mdelay(100);
+ reg_pair[3].val = &ch_a_eq[i];
+ reg_pair[4].val = &ch_a_ctl2[j];
+ reg_pair[5].val = &ch_b_eq[i];
+ reg_pair[6].val = &ch_b_ctl2[j];
+
+ for (k = 0; k < 10; k++) {
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(i2c_addr[dpmac],
+ reg_pair[k].addr,
+ 1, reg_pair[k].val, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0,
+ i2c_addr[dpmac],
+ 1, &udev);
+ if (!ret)
+ ret = dm_i2c_write(udev,
+ reg_pair[k].addr,
+ reg_pair[k].val, 1);
+#endif
+ if (ret)
+ goto error;
+ }
+
ret = miiphy_read(dev, phy_addr, 0x11, &value);
if (ret > 0)
goto error;
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index 4387862..8b62bbe 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -46,7 +46,9 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_DDR_CLK_FREQ 100000000
#else
#define CONFIG_QIXIS_I2C_ACCESS
+#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C_EARLY_INIT
+#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#endif
@@ -357,9 +359,7 @@ unsigned long get_board_ddr_clk(void);
* RTC configuration
*/
#define RTC
-#define CONFIG_RTC_PCF8563 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
-#define CONFIG_CMD_DATE
/* EEPROM */
#define CONFIG_ID_EEPROM
--
2.9.5
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