[U-Boot] [PATCH v2 10/11] riscv: qemu: add SPL configuration
Anup Patel
anup at brainfault.org
Mon Jul 29 08:41:15 UTC 2019
On Sun, Jul 28, 2019 at 9:32 PM Lukas Auer
<lukas.auer at aisec.fraunhofer.de> wrote:
>
> Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL
> enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The
> configurations are meant to help the development of SPL on RISC-V.
>
> The configurations enable RAM as the only SPL boot device. Images must
> be loaded at address 0x80200000. In the default boot flow, U-Boot SPL
> starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot
> proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is
> then started in supervisor mode by OpenSBI.
>
> Signed-off-by: Lukas Auer <lukas.auer at aisec.fraunhofer.de>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
> Tested-by: Bin Meng <bmeng.cn at gmail.com>
> ---
>
> Changes in v2: None
>
> board/emulation/qemu-riscv/Kconfig | 10 ++++++++++
> board/emulation/qemu-riscv/MAINTAINERS | 2 ++
> board/emulation/qemu-riscv/qemu-riscv.c | 17 +++++++++++++++++
> configs/qemu-riscv32_spl_defconfig | 11 +++++++++++
> configs/qemu-riscv64_spl_defconfig | 12 ++++++++++++
> include/configs/qemu-riscv.h | 14 ++++++++++++++
> 6 files changed, 66 insertions(+)
> create mode 100644 configs/qemu-riscv32_spl_defconfig
> create mode 100644 configs/qemu-riscv64_spl_defconfig
>
> diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
> index 6cc7c31dc6..1928d6dda0 100644
> --- a/board/emulation/qemu-riscv/Kconfig
> +++ b/board/emulation/qemu-riscv/Kconfig
> @@ -13,13 +13,21 @@ config SYS_CONFIG_NAME
> default "qemu-riscv"
>
> config SYS_TEXT_BASE
> + default 0x81200000 if SPL
> default 0x80000000 if !RISCV_SMODE
> default 0x80200000 if RISCV_SMODE && ARCH_RV64I
> default 0x80400000 if RISCV_SMODE && ARCH_RV32I
>
> +config SPL_TEXT_BASE
> + default 0x80000000
> +
> +config SPL_OPENSBI_LOAD_ADDR
> + default 0x81000000
> +
> config BOARD_SPECIFIC_OPTIONS # dummy
> def_bool y
> select GENERIC_RISCV
> + select SUPPORT_SPL
> imply SYS_NS16550
> imply VIRTIO_MMIO
> imply VIRTIO_NET
> @@ -43,5 +51,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> imply CMD_PCI
> imply E1000
> imply NVME
> + imply SPL_RAM_SUPPORT
> + imply SPL_RAM_DEVICE
>
> endif
> diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS
> index c701c83d77..78969ed6bd 100644
> --- a/board/emulation/qemu-riscv/MAINTAINERS
> +++ b/board/emulation/qemu-riscv/MAINTAINERS
> @@ -5,5 +5,7 @@ F: board/emulation/qemu-riscv/
> F: include/configs/qemu-riscv.h
> F: configs/qemu-riscv32_defconfig
> F: configs/qemu-riscv32_smode_defconfig
> +F: configs/qemu-riscv32_spl_defconfig
> F: configs/qemu-riscv64_defconfig
> F: configs/qemu-riscv64_smode_defconfig
> +F: configs/qemu-riscv64_spl_defconfig
> diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c
> index d6167aaef1..e04bd3001c 100644
> --- a/board/emulation/qemu-riscv/qemu-riscv.c
> +++ b/board/emulation/qemu-riscv/qemu-riscv.c
> @@ -6,6 +6,7 @@
> #include <common.h>
> #include <dm.h>
> #include <fdtdec.h>
> +#include <spl.h>
> #include <virtio_types.h>
> #include <virtio.h>
>
> @@ -87,3 +88,19 @@ int ft_board_setup(void *blob, bd_t *bd)
>
> return 0;
> }
> +
> +#ifdef CONFIG_SPL
> +u32 spl_boot_device(void)
> +{
> + /* RISC-V QEMU only supports RAM as SPL boot device */
> + return BOOT_DEVICE_RAM;
> +}
> +#endif
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> + /* boot using first FIT config */
> + return 0;
> +}
> +#endif
> diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig
> new file mode 100644
> index 0000000000..78e755b36a
> --- /dev/null
> +++ b/configs/qemu-riscv32_spl_defconfig
> @@ -0,0 +1,11 @@
> +CONFIG_RISCV=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_SPL=y
> +CONFIG_TARGET_QEMU_VIRT=y
> +CONFIG_RISCV_SMODE=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_FIT=y
> +CONFIG_DISPLAY_CPUINFO=y
> +CONFIG_DISPLAY_BOARDINFO=y
> +# CONFIG_CMD_MII is not set
> +CONFIG_OF_PRIOR_STAGE=y
> diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
> new file mode 100644
> index 0000000000..a3f5e29d58
> --- /dev/null
> +++ b/configs/qemu-riscv64_spl_defconfig
> @@ -0,0 +1,12 @@
> +CONFIG_RISCV=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_SPL=y
> +CONFIG_TARGET_QEMU_VIRT=y
> +CONFIG_ARCH_RV64I=y
> +CONFIG_RISCV_SMODE=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_FIT=y
> +CONFIG_DISPLAY_CPUINFO=y
> +CONFIG_DISPLAY_BOARDINFO=y
> +# CONFIG_CMD_MII is not set
> +CONFIG_OF_PRIOR_STAGE=y
> diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
> index df22f780b0..69aa82d36a 100644
> --- a/include/configs/qemu-riscv.h
> +++ b/include/configs/qemu-riscv.h
> @@ -8,6 +8,18 @@
>
> #include <linux/sizes.h>
>
> +#ifdef CONFIG_SPL
> +
> +#define CONFIG_SPL_MAX_SIZE 0x00100000
> +#define CONFIG_SPL_BSS_START_ADDR 0x84000000
> +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
> +#define CONFIG_SYS_SPL_MALLOC_START 0x84100000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
> +
> +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
> +
> +#endif
> +
> #define CONFIG_SYS_SDRAM_BASE 0x80000000
> #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
>
> @@ -22,6 +34,7 @@
> /* Environment options */
> #define CONFIG_ENV_SIZE SZ_128K
>
> +#ifndef CONFIG_SPL_BUILD
> #define BOOT_TARGET_DEVICES(func) \
> func(QEMU, qemu, na) \
> func(VIRTIO, virtio, 0) \
> @@ -51,5 +64,6 @@
> #define CONFIG_PREBOOT \
> "setenv fdt_addr ${fdtcontroladdr};" \
> "fdt addr ${fdtcontroladdr};"
> +#endif
>
> #endif /* __CONFIG_H */
> --
> 2.21.0
>
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> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
Reviewed-by: Anup Patel <anup.patel at wdc.com>
Regards,
Anup
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