[U-Boot] [PATCH v2 00/11] SPL support for RISC-V
Anup Patel
anup at brainfault.org
Mon Jul 29 08:44:08 UTC 2019
On Sun, Jul 28, 2019 at 9:27 PM Lukas Auer
<lukas.auer at aisec.fraunhofer.de> wrote:
>
> This series adds support for SPL to RISC-V U-Boot. Images can be booted
> via OpenSBI (FW_DYNAMIC firmware) or by directly jumping to them. In the
> former case, OpenSBI and U-Boot proper are bundled as a FIT image and
> made available to U-Boot SPL. Currently, only the QEMU board enables
> U-Boot SPL with a dedicated configuration. It uses RAM as SPL boot
> device.
>
> On many RISC-V CPUs, the device tree is provided to U-Boot by the
> first stage bootloader. This requires changes to U-Boot SPL (patches 1,
> 2 and 3), which modify the behavior on other boards as well.
>
> To test this series, OpenSBI has to be compiled first. The
> fw_dynamic.bin binary must be copied into the U-Boot root directory.
> Alternatively, the location of the binary can be specified with the
> OPENSBI environment variable. U-Boot can then be build as normal using
> the configuration qemu-riscv64_spl_defconfig for 64-bit builds or
> qemu-riscv32_spl_defconfig for 32-bit builds. The outputs from the build
> process are the U-Boot SPL binary (spl/u-boot-spl.bin) and the U-Boot
> FIT image (u-boot.itb) containing U-Boot proper and OpenSBI.
>
> U-Boot can be run in QEMU with the following command.
>
> qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \
> -device loader,file=u-boot.itb,addr=0x80200000
>
> Changes in v2:
> - Rebase on master and format documentation as reStructuredText
>
> Lukas Auer (11):
> fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL
> Makefile: support building SPL FIT images without device trees
> spl: fit: use U-Boot device tree when FIT image has no device tree
> riscv: add run mode configuration for SPL
> spl: support booting via RISC-V OpenSBI
> riscv: add SPL support
> riscv: support SPL stack and global data relocation
> riscv: add a generic FIT generator script
> riscv: set default FIT generator script and build target for SPL
> builds
> riscv: qemu: add SPL configuration
> doc: update QEMU RISC-V documentation
>
> Kconfig | 4 +-
> Makefile | 8 +-
> arch/Kconfig | 6 ++
> arch/riscv/Kconfig | 36 +++++++--
> arch/riscv/cpu/ax25/Kconfig | 6 +-
> arch/riscv/cpu/cpu.c | 6 +-
> arch/riscv/cpu/generic/Kconfig | 5 +-
> arch/riscv/cpu/start.S | 62 ++++++++++++++-
> arch/riscv/cpu/u-boot-spl.lds | 82 +++++++++++++++++++
> arch/riscv/include/asm/encoding.h | 2 +-
> arch/riscv/include/asm/spl.h | 31 ++++++++
> arch/riscv/lib/Makefile | 8 +-
> arch/riscv/lib/mkimage_fit_opensbi.sh | 100 ++++++++++++++++++++++++
> arch/riscv/lib/spl.c | 48 ++++++++++++
> board/emulation/qemu-riscv/Kconfig | 10 +++
> board/emulation/qemu-riscv/MAINTAINERS | 2 +
> board/emulation/qemu-riscv/qemu-riscv.c | 17 ++++
> common/image.c | 1 +
> common/spl/Kconfig | 17 ++++
> common/spl/Makefile | 1 +
> common/spl/spl.c | 8 +-
> common/spl/spl_fit.c | 37 ++++++---
> common/spl/spl_opensbi.c | 85 ++++++++++++++++++++
> configs/qemu-riscv32_spl_defconfig | 11 +++
> configs/qemu-riscv64_spl_defconfig | 12 +++
> doc/board/emulation/qemu-riscv.rst | 60 +++++++++++++-
> include/configs/qemu-riscv.h | 14 ++++
> include/fdtdec.h | 2 +-
> include/image.h | 1 +
> include/opensbi.h | 40 ++++++++++
> include/spl.h | 5 ++
> lib/fdtdec.c | 6 +-
> 32 files changed, 691 insertions(+), 42 deletions(-)
> create mode 100644 arch/riscv/cpu/u-boot-spl.lds
> create mode 100644 arch/riscv/include/asm/spl.h
> create mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh
> create mode 100644 arch/riscv/lib/spl.c
> create mode 100644 common/spl/spl_opensbi.c
> create mode 100644 configs/qemu-riscv32_spl_defconfig
> create mode 100644 configs/qemu-riscv64_spl_defconfig
> create mode 100644 include/opensbi.h
>
> --
> 2.21.0
>
Hi Lukas,
Amazing work !!!
Very nice and clean...
I will try to play around with it on QEMU.
Thanks & Regards,
Anup
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