[U-Boot] [PATCH 6/6] riscv: ax25: use CCTL to flush d-cache

[Bin Meng]

Hi Rick,

On Tue, May 28, 2019 at 5:45 PM Andes <uboot at andestech.com> wrote:
>
> From: Rick Chen <rick at andestech.com>
>
> Use CCTL command to do d-cache write back and invalidate
> instead of fence.
>
> Signed-off-by: Rick Chen <rick at andestech.com>
> Cc: Greentime Hu <greentime at andestech.com>
> ---
>  arch/riscv/cpu/ax25/cache.c | 22 +++++++++++++---------
>  1 file changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
> index 228fc55..d30071e 100644
> --- a/arch/riscv/cpu/ax25/cache.c
> +++ b/arch/riscv/cpu/ax25/cache.c
> @@ -5,17 +5,21 @@
>   */
>
>  #include <common.h>
> +#include <asm/csr.h>
> +
> +#ifdef CONFIG_RISCV_NDS_CACHE
> +/* mcctlcommand */
> +#define CCTL_REG_MCCTLCOMMAND_NUM      0x7cc
> +
> +/* D-cache operation */
> +#define CCTL_L1D_WBINVAL_ALL   6
> +#endif
>
>  void flush_dcache_all(void)
>  {
> -       /*
> -        * Andes' AX25 does not have a coherence agent. U-Boot must use data
> -        * cache flush and invalidate functions to keep data in the system
> -        * coherent.
> -        * The implementation of the fence instruction in the AX25 flushes the
> -        * data cache and is used for this purpose.
> -        */
> -       asm volatile ("fence" ::: "memory");
> +#ifdef CONFIG_RISCV_NDS_CACHE
> +       csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);

I think CCTL_REG_MCCTLCOMMAND_NUM is a vendor specific CSR. Does
upstream GCC support this CSR?

> +#endif
>  }
>
>  void flush_dcache_range(unsigned long start, unsigned long end)
> @@ -72,8 +76,8 @@ void dcache_disable(void)
>  {
>  #ifndef CONFIG_SYS_DCACHE_OFF
>  #ifdef CONFIG_RISCV_NDS_CACHE
> +       csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
>         asm volatile (
> -               "fence\n\t"
>                 "csrr t1, mcache_ctl\n\t"
>                 "andi t0, t1, ~0x2\n\t"
>                 "csrw mcache_ctl, t0\n\t"
> --

Regards,
Bin