[U-Boot] [PATCH v2 1/7] armv8: lx2160a: The lx2160a platform supports the I2C driver model.
Chuanhua Han
chuanhua.han at nxp.com
Wed Jun 12 08:39:00 UTC 2019
DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C
API when DM_I2C is used.When DM_I2C_COMPAT is not enabled for
compilation, a compilation error will be generated. This patch solves
the problem that the i2c-related api of the lx2160a platform does not
support dm.
Signed-off-by: Chuanhua Han <chuanhua.han at nxp.com>
---
Changes in v2:
- No change.
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 ---
board/freescale/common/emc2305.c | 21 ++++++
board/freescale/common/qixis.c | 17 +++++
board/freescale/common/sys_eeprom.c | 84 +++++++++++++++++++++--
board/freescale/common/vid.c | 84 +++++++++++++++++++++++
board/freescale/lx2160a/lx2160a.c | 8 +++
drivers/ddr/fsl/main.c | 36 +++++++++-
7 files changed, 245 insertions(+), 13 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a843c1eb65..f3eaab960b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -234,14 +234,6 @@ config ARCH_LX2160A
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
- select SYS_I2C_MXC_I2C1
- select SYS_I2C_MXC_I2C2
- select SYS_I2C_MXC_I2C3
- select SYS_I2C_MXC_I2C4
- select SYS_I2C_MXC_I2C5
- select SYS_I2C_MXC_I2C6
- select SYS_I2C_MXC_I2C7
- select SYS_I2C_MXC_I2C8
imply DISTRO_DEFAULTS
imply PANIC_HANG
imply SCSI
diff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c
index 8523084da9..b1ca051db2 100644
--- a/board/freescale/common/emc2305.c
+++ b/board/freescale/common/emc2305.c
@@ -24,10 +24,22 @@ void set_fan_speed(u8 data)
I2C_EMC2305_FAN5};
for (index = 0; index < NUM_OF_FANS; index++) {
+#ifndef CONFIG_DM_I2C
if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, &data, 1) != 0) {
printf("Error: failed to change fan speed @%x\n",
Fan[index]);
}
+#else
+ struct udevice *dev;
+
+ if (i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev))
+ continue;
+
+ if (dm_i2c_write(dev, Fan[index], &data, 1) != 0) {
+ printf("Error: failed to change fan speed @%x\n",
+ Fan[index]);
+ }
+#endif
}
}
@@ -36,6 +48,15 @@ void emc2305_init(void)
u8 data;
data = I2C_EMC2305_CMD;
+#ifndef CONFIG_DM_I2C
if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, &data, 1) != 0)
printf("Error: failed to configure EMC2305\n");
+#else
+ struct udevice *dev;
+
+ if (!i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev))
+ if (dm_i2c_write(dev, I2C_EMC2305_CONF, &data, 1))
+ printf("Error: failed to configure EMC2305\n");
+#endif
+
}
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index f1b98bcd2a..2c4c4ae108 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -24,13 +24,30 @@
#ifdef CONFIG_SYS_I2C_FPGA_ADDR
u8 qixis_read_i2c(unsigned int reg)
{
+#ifndef CONFIG_DM_I2C
return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
+#else
+ struct udevice *dev;
+
+ if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
+ return 0xff;
+
+ return dm_i2c_reg_read(dev, reg);
+#endif
}
void qixis_write_i2c(unsigned int reg, u8 value)
{
u8 val = value;
+#ifndef CONFIG_DM_I2C
i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
+#else
+ struct udevice *dev;
+
+ if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
+ dm_i2c_reg_write(dev, reg, val);
+#endif
+
}
#endif
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index ab0fe0baf1..ff76cef411 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -148,23 +148,42 @@ static int read_eeprom(void)
{
int ret;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#ifndef CONFIG_DM_I2C
unsigned int bus;
+#endif
#endif
if (has_been_read)
return 0;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#ifndef CONFIG_DM_I2C
bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
+#endif
- ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
- (void *)&e, sizeof(e));
+#ifndef CONFIG_DM_I2C
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ (void *)&e, sizeof(e));
+#else
+ struct udevice *dev;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+ CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);
+#else
+ ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);
+#endif
+ if (!ret)
+ ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e));
+#endif
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#ifndef CONFIG_DM_I2C
i2c_set_bus_num(bus);
#endif
+#endif
#ifdef DEBUG
show_eeprom();
@@ -198,7 +217,9 @@ static int prog_eeprom(void)
int i;
void *p;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#ifndef CONFIG_DM_I2C
unsigned int bus;
+#endif
#endif
/* Set the reserved values to 0xFF */
@@ -210,9 +231,11 @@ static int prog_eeprom(void)
#endif
update_crc();
+#ifndef CONFIG_DM_I2C
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
#endif
/*
@@ -221,8 +244,26 @@ static int prog_eeprom(void)
* complete a given write.
*/
for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
- ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
p, min((int)(sizeof(e) - i), 8));
+#else
+ struct udevice *dev;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ &dev);
+#else
+ ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ &dev);
+#endif
+ if (!ret)
+ ret = dm_i2c_write(dev, i, p, min((int)(sizeof(e) - i),
+ 8));
+#endif
if (ret)
break;
udelay(5000); /* 5ms write cycle timing */
@@ -232,14 +273,33 @@ static int prog_eeprom(void)
/* Verify the write by reading back the EEPROM and comparing */
struct eeprom e2;
+#ifndef CONFIG_DM_I2C
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2));
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ (void *)&e2, sizeof(e2));
+#else
+ struct udevice *dev;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ &dev);
+#else
+ ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ &dev);
+#endif
+ if (!ret)
+ ret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2));
+#endif
if (!ret && memcmp(&e, &e2, sizeof(e)))
ret = -1;
}
+#ifndef CONFIG_DM_I2C
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
+#endif
#endif
if (ret) {
@@ -528,8 +588,24 @@ unsigned int get_cpu_board_revision(void)
u8 minor; /* 0x05 Board revision, minor */
} be;
+#ifndef CONFIG_DM_I2C
i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(void *)&be, sizeof(be));
+#else
+ struct udevice *dev;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ &dev);
+#else
+ ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ &dev)
+#endif
+ if (!ret)
+ dm_i2c_read(dev, 0, (void *)&be, sizeof(be));
+#endif
if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))
return MPC85XX_CPU_BOARD_REV(0, 0);
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 0ca389c9ae..49b4cd14f9 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -60,13 +60,23 @@ static int find_ir_chip_on_i2c(void)
u8 byte;
int i;
const int ir_i2c_addr[] = {0x38, 0x08, 0x09};
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
/* Check all the address */
for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) {
i2caddress = ir_i2c_addr[i];
+#ifndef CONFIG_DM_I2C
ret = i2c_read(i2caddress,
IR36021_MFR_ID_OFFSET, 1, (void *)&byte,
sizeof(byte));
+#else
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET,
+ (void *)&byte, sizeof(byte));
+#endif
if ((ret >= 0) && (byte == IR36021_MFR_ID))
return i2caddress;
}
@@ -102,11 +112,21 @@ static int read_voltage_from_INA220(int i2caddress)
int i, ret, voltage_read = 0;
u16 vol_mon;
u8 buf[2];
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
for (i = 0; i < NUM_READINGS; i++) {
+#ifndef CONFIG_DM_I2C
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
I2C_VOL_MONITOR_BUS_V_OFFSET, 1,
(void *)&buf, 2);
+#else
+ ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET,
+ (void *)&buf, 2);
+#endif
if (ret) {
printf("VID: failed to read core voltage\n");
return ret;
@@ -135,11 +155,21 @@ static int read_voltage_from_IR(int i2caddress)
int i, ret, voltage_read = 0;
u16 vol_mon;
u8 buf;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
for (i = 0; i < NUM_READINGS; i++) {
+#ifndef CONFIG_DM_I2C
ret = i2c_read(i2caddress,
IR36021_LOOP1_VOUT_OFFSET,
1, (void *)&buf, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET,
+ (void *)&buf, 1);
+#endif
if (ret) {
printf("VID: failed to read vcpu\n");
return ret;
@@ -178,17 +208,33 @@ static int read_voltage_from_LTC(int i2caddress)
int ret, vcode = 0;
u8 chan = PWM_CHANNEL0;
+#ifndef CONFIG_DM_I2C
/* select the PAGE 0 using PMBus commands PAGE for VDD*/
ret = i2c_write(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_PAGE, 1, &chan, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1);
+#endif
if (ret) {
printf("VID: failed to select VDD Page 0\n");
return ret;
}
+#ifndef CONFIG_DM_I2C
/*read the output voltage using PMBus command READ_VOUT*/
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
+#else
+ ret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
+ if (ret) {
+ printf("VID: failed to read the volatge\n");
+ return ret;
+ }
+#endif
if (ret) {
printf("VID: failed to read the volatge\n");
return ret;
@@ -293,8 +339,18 @@ static int set_voltage_to_IR(int i2caddress, int vdd)
vid = DIV_ROUND_UP(vdd - 245, 5);
#endif
+#ifndef CONFIG_DM_I2C
ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
1, (void *)&vid, sizeof(vid));
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET,
+ (void *)&vid, sizeof(vid));
+
+#endif
if (ret) {
printf("VID: failed to write VID\n");
return -1;
@@ -330,8 +386,17 @@ static int set_voltage_to_LTC(int i2caddress, int vdd)
vdd & 0xFF, (vdd & 0xFF00) >> 8};
/* Write the desired voltage code to the regulator */
+#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
+ (void *)&buff, 5);
+#endif
if (ret) {
printf("VID: I2C failed to write to the volatge regulator\n");
return -1;
@@ -515,14 +580,24 @@ int adjust_vdd(ulong vdd_override)
}
/* check IR chip work on Intel mode*/
+#ifndef CONFIG_DM_I2C
ret = i2c_read(i2caddress,
IR36021_INTEL_MODE_OOFSET,
1, (void *)&buf, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
+ (void *)&buf, 1);
+#endif
if (ret) {
printf("VID: failed to read IR chip mode.\n");
ret = -1;
goto exit;
}
+
if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
printf("VID: IR Chip is not used in Intel mode.\n");
ret = -1;
@@ -687,9 +762,18 @@ int adjust_vdd(ulong vdd_override)
}
/* check IR chip work on Intel mode*/
+#ifndef CONFIG_DM_I2C
ret = i2c_read(i2caddress,
IR36021_INTEL_MODE_OOFSET,
1, (void *)&buf, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
+ (void *)&buf, 1);
+#endif
if (ret) {
printf("VID: failed to read IR chip mode.\n");
ret = -1;
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 6109b280c6..ea28bfb621 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -74,7 +74,15 @@ int select_i2c_ch_pca9547(u8 ch)
{
int ret;
+#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, 0, &ch, 1);
+#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index e1f69a1d25..ac0783b428 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -92,7 +92,10 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
uint8_t dummy = 0;
#endif
+#ifndef CONFIG_DM_I2C
i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
+#endif
+
#ifdef CONFIG_SYS_FSL_DDR4
/*
@@ -101,6 +104,7 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
* To access the upper 256 bytes, we need to set EE page address to 1
* See Jedec standar No. 21-C for detail
*/
+#ifndef CONFIG_DM_I2C
i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
if (!ret) {
@@ -111,8 +115,38 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
(int)sizeof(generic_spd_eeprom_t) - 256));
}
#else
+ struct udevice *dev;
+ int read_len = min(256, (int)sizeof(generic_spd_eeprom_t) - 256);
+
+ ret = i2c_get_chip_for_busnum(0, SPD_SPA0_ADDRESS, 1, &dev);
+ if (!ret)
+ dm_i2c_write(dev, 0, &dummy, 1);
+ ret = i2c_get_chip_for_busnum(0, i2c_address, 1, &dev);
+ if (!ret) {
+ if (!dm_i2c_read(dev, 0, (uchar *)spd, 256)) {
+ if (!i2c_get_chip_for_busnum(0, SPD_SPA1_ADDRESS,
+ 1, &dev))
+ dm_i2c_write(dev, 0, &dummy, 1);
+ if (!i2c_get_chip_for_busnum(0, i2c_address, 1, &dev))
+ ret = dm_i2c_read(dev, 0,
+ (uchar *)((ulong)spd + 256),
+ read_len);
+ }
+ }
+#endif
+
+#else
+
+#ifndef CONFIG_DM_I2C
ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
- sizeof(generic_spd_eeprom_t));
+ sizeof(generic_spd_eeprom_t));
+#else
+ ret = i2c_get_chip_for_busnum(0, i2c_address, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, 0, (uchar *)spd,
+ sizeof(generic_spd_eeprom_t));
+#endif
+
#endif
if (ret) {
--
2.17.1
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