[U-Boot] Functional clashes between vanilla and Yocto releases
erosca at de.adit-jv.com
Tue Jun 18 11:15:43 UTC 2019
Hello Marek, hello Yokoyama-san,
Reviewing the Renesas Yocto v3.19/3.21 U-Boot updates, I came across a
few patches which conflict with features in vanilla both conceptually
Making a local conflict resolution is not future-proof. That's why
I would like to kindly ask for your long-term view and feedback.
I have two topics, one relatively major and one relatively minor.
A. Getting platform information (e.g. DRAM, board id) from ATF.
A.1. Vanilla ATF already passes DRAM information via the first four
general-purpose registers x0...x3 of the primary CPU when control
is given to U-Boot. The relevant commits are shown in .
A.2. Renesas Yocto release achieves a similar goal very differently.
Currently, Renesas ATF implements a dedicated SMC call which is then
used by U-Boot to get the board id. The latter is read from the EEPROM
of the ROHM BD9571 PMIC, available on the reference targets.
The relevant commits implementing the feature are shown in .
It looks like the two approaches try to serve the same purpose, so is
there a chance from your point of view to make an alignment?
B. The Renesas commits listed in  talk about a "DMA controller
restriction of SDHI". I have a few questions/remarks:
- Is the restriction described anywhere in the ERRATA documents?
It would have been incredibly useful to see this information
present in the commit description.
- My guess is that increasing the cache line size from 64 to 128 bytes
U-Boot-wide is not the best solution to fix a restriction of one
specific HW IP in the SoC. Do you foresee a cleaner way to tackle it?
Thank you very much!
 Commits implementing feature A.1.
("plat: rcar: Pass DTB with DRAM layout from BL2 to next stages")
("ARM: renesas: Save boot parameters passed in by ATF")
("ARM: renesas: Configure DRAM size from ATF DT fragment")
("ARM: renesas: Factor out DRAM setup on R-Car Gen3")
 Commits implementing feature A.2.
("plat: rcar: BL31: Add SiP for getting board ID")
("board: salvator-x: Add function to activate with suitable DT")
("board: ebisu: Add function to activate with suitable DT")
("board: ulcb: Add function to activate with suitable DT")
 Commits fixing "DMA controller restriction of SDHI" on Gen3
("mmc: tmio: rcar_gen3: Add DMA transfer address alignment check at writing")
("ARM: rcar_gen3: Change to SYS_CACHE_SHIFT_7")
More information about the U-Boot