[U-Boot] [PATCH v5 14/18] clk: sandbox: Adjust clk-divider to emulate reading its value from HW

[Lukasz Majewski]

The generic divider clock code for CCF requires reading the divider value
from HW registers. As sandbox by design has readl() as no-op it was
necessary to provide this value in the other way.

The new field in the divider structure (accessible only when sandbox is
run) has been introduced for this purpose.

Signed-off-by: Lukasz Majewski <lukma at denx.de>
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None

 drivers/clk/clk-divider.c    | 10 +++++++++-
 include/linux/clk-provider.h |  3 +++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 3348d97829..6921c76a48 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -74,7 +74,12 @@ static ulong clk_divider_recalc_rate(struct clk *clk)
 	unsigned long parent_rate = clk_get_parent_rate(clk);
 	unsigned int val;
 
-	val = readl(divider->reg) >> divider->shift;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+	val = divider->io_divider_val;
+#else
+	val = readl(divider->reg);
+#endif
+	val >>= divider->shift;
 	val &= clk_div_mask(divider->width);
 
 	return divider_recalc_rate(clk, parent_rate, val, divider->table,
@@ -112,6 +117,9 @@ static struct clk *_register_divider(struct device *dev, const char *name,
 	div->width = width;
 	div->flags = clk_divider_flags;
 	div->table = table;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+	div->io_divider_val = *(u32 *)reg;
+#endif
 
 	/* register the clock */
 	clk = &div->clk;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index e06487f07b..53c9c41b90 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -75,6 +75,9 @@ struct clk_divider {
 	u8		width;
 	u8		flags;
 	const struct clk_div_table	*table;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+	u32             io_divider_val;
+#endif
 };
 
 #define clk_div_mask(width)	((1 << (width)) - 1)
-- 
2.11.0