[U-Boot] [PATCH v3 2/2] xilinx_xiic: Fix transfer initialisation
Melin Tomas
tomas.melin at vaisala.com
Fri Jun 28 12:13:20 UTC 2019
Hi,
On 6/28/19 3:08 PM, Melin Tomas wrote:
> Prior to starting a new transfer, conditionally wait for bus to not
> be busy.
>
> Reinitialise controller as otherwise operation is not stable.
> For reference, see linux kernel commit: 9656eeebf3f1 ("i2c: Revert
> "i2c: xiic: Do not reset controller before every transfer"")
>
> Signed-off-by: Tomas Melin <tomas.melin at vaisala.com>
> ---
>
> Changes in v2:
> - Change variable declaration order
> - Change timeout to 3ms
>
> Changes in v3:
> - Change timeout to 1000ms
> - Add print in case of timeout
>
> drivers/i2c/xilinx_xiic.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/i2c/xilinx_xiic.c b/drivers/i2c/xilinx_xiic.c
> index e4ca0ab936..afb5f21b75 100644
> --- a/drivers/i2c/xilinx_xiic.c
> +++ b/drivers/i2c/xilinx_xiic.c
> @@ -266,8 +266,20 @@ static void xiic_reinit(struct xilinx_xiic_priv *priv)
>
> static int xilinx_xiic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
> {
> + struct xilinx_xiic_priv *priv = dev_get_priv(dev);
> int ret = 0;
>
> + ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
> + XIIC_SR_BUS_BUSY_MASK, false, 1000, true);
> +
> + if (ret == -ETIMEDOUT)
> + dev_err(dev, "timeout waiting for bus not busy condition");
If patch otherwise ok, please amend this line before applying by adding
missing '\n'.
if required, I can ofcourse send a v4.
thanks,
Tomas
> +
> + if (ret)
> + return ret;
> +
> + xiic_reinit(priv);
> +
> for (; nmsgs > 0; nmsgs--, msg++) {
> if (msg->flags & I2C_M_RD)
> ret = xilinx_xiic_read_common(dev, msg, nmsgs);
More information about the U-Boot
mailing list