[U-Boot] [PATCH 3/4] usb: xhci-dwc3: Add USB2 PHY configuration
Kever Yang
kever.yang at rock-chips.com
Sun Jun 30 13:31:29 UTC 2019
Hi Mark,
I add Marek and Bin Meng for this patch, I'm not sure where
are these phy setting should go.
Thanks,
- Kever
On 06/30/2019 12:29 AM, Mark Kettenis wrote:
> Configure USB2 PHY register based on "phy_type" property and
> handle all the quirks that are relevant for Rockchip RK3399 SoCs.
>
> Signed-off-by: Mark Kettenis <kettenis at openbsd.org>
> ---
> drivers/usb/host/xhci-dwc3.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
> index 83b9f119e7..ed955dc8b8 100644
> --- a/drivers/usb/host/xhci-dwc3.c
> +++ b/drivers/usb/host/xhci-dwc3.c
> @@ -118,6 +118,8 @@ static int xhci_dwc3_probe(struct udevice *dev)
> struct dwc3 *dwc3_reg;
> enum usb_dr_mode dr_mode;
> struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
> + const char *phy;
> + u32 reg;
> int ret;
>
> hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
> @@ -132,6 +134,24 @@ static int xhci_dwc3_probe(struct udevice *dev)
>
> dwc3_core_init(dwc3_reg);
>
> + /* Set dwc3 usb2 phy config */
> + reg = readl(&dwc3_reg->g_usb2phycfg[0]);
> +
> + phy = dev_read_string(dev, "phy_type");
> + if (phy && strcmp(phy, "utmi_wide") == 0) {
> + reg |= DWC3_GUSB2PHYCFG_PHYIF;
> + reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
> + reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
> + }
> +
> + if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
> + reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
> +
> + if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
> + reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
> +
> + writel(reg, &dwc3_reg->g_usb2phycfg[0]);
> +
> dr_mode = usb_get_dr_mode(dev_of_offset(dev));
> if (dr_mode == USB_DR_MODE_UNKNOWN)
> /* by default set dual role mode to HOST */
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