[U-Boot] [PATCH 3/3] arm: socfpga: put initial U-Boot stack into DDR
Marek Vasut
marex at denx.de
Fri Mar 1 11:42:26 UTC 2019
On 3/1/19 8:55 AM, Simon Goldschmidt wrote:
> On Thu, Feb 28, 2019 at 10:44 PM Marek Vasut <marex at denx.de> wrote:
>>
>> On 2/28/19 9:33 PM, Simon Goldschmidt wrote:
>>> If SPL pre-reloc stage puts the stack into DDR, U-Boot should be able to
>>> do that, too.
>>
>> Here you mention SPL pre-reloc stage, while about mid-way through the
>> patch you have a comment talking about SPL post-reloc stage, which one
>> is it ? I think the commit message needs rewording, it's not clear what
>> the patch does based on it.
>
> Ehrm right. The commit message is wrong. Post-reloc is correct.
>
>> On a separate note, this is likely a fix for current release, right ?
>
> Not really. For A10, this should not change anything, just ensure the common
> header file does not use 2 different ways to achieve the same thing.
> Note that A10 does *not* enable a different stack/malloc area for SPL
> post-reloc!
OK
> For gen5, yes there is a change, but only in U-Boot, not in SPL. But this is
> not a fix, it's an improvement to be able to make the SPL malloc pool smaller
> without U-Boot overwriting it. It's currently not overwritten as both
> malloc sizes
> are the same. I'd change that in a follow-up patch which reduces SPL malloc
> size for gen5.
Sounds good
>> Finally , keep in mind the A10 needs to load the FPGA before DRAM
>> becomes available, so the stack shenanigans there become even more nasty.
>
> Right, that's why even the initial malloc size for SPL is 64 KiB,
> right? As written
> above, this patch should not change anything for A10, so this should still work.
No, that's because the A10 does a lot of allocations in SPL iirc.
> From reading the A10 SPL code, I didn't quite get how this works though, as
> it seems the simple-malloc members in gd are only initialized after
> spl_early_init(), so after initializing DT/DM? Or is A10 not yet
> converted to DT?
It's semi-converted. The early part still needs some work.
> Regards,
> Simon
>
>>> The reason to do so is that this way, U-Boot initial stack can be larger
>>> than SPL initial stack. In situations where we want to save the SPL
>>> in SRAM for next boot without reloading, this prevents overwriting the
>>> SPL DTB in SRAM if U-Boot stack usage gets too high.
>>>
>>> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
>>> ---
>>>
>>> include/configs/socfpga_common.h | 20 +++++++++++++-------
>>> 1 file changed, 13 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
>>> index c23b34186a..7ae3db233f 100644
>>> --- a/include/configs/socfpga_common.h
>>> +++ b/include/configs/socfpga_common.h
>>> @@ -38,12 +38,23 @@
>>> #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
>>> (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
>>> CONFIG_SYS_INIT_RAM_SIZE)))
>>> -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_BOOTCOUNT_ADDR
>>> +#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
>>> #else
>>> -#define CONFIG_SYS_INIT_SP_ADDR \
>>> +#define CONFIG_SPL_STACK \
>>> (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
>>> #endif
>>>
>>> +/*
>>> + * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
>>> + * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
>>> + * in U-Boot pre-reloc is higher than in SPL.
>>> + */
>>> +#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
>>> +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
>>> +#else
>>> +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
>>> +#endif
>>> +
>>> #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
>>>
>>> /*
>>> @@ -274,11 +285,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>>> #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
>>> #endif
>>>
>>> -/*
>>> - * Stack setup
>>> - */
>>> -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
>>> -
>>> /* Extra Environment */
>>> #ifndef CONFIG_SPL_BUILD
>>>
>>>
>>
>>
>> --
>> Best regards,
>> Marek Vasut
--
Best regards,
Marek Vasut
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