[U-Boot] [PATCH] ARM: socfpga: configure pl310 from dts

[Dinh Nguyen]

Read the cache properties of the L2 cache controller from the device
tree and configure it.

Signed-off-by: Dinh Nguyen <dinguyen at kernel.org>
---
 arch/arm/include/asm/pl310.h |  4 ++++
 arch/arm/mach-socfpga/misc.c | 45 +++++++++++++++++++++++++++++-------
 2 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index b83978b1cc..346dbe476d 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -19,6 +19,10 @@
 #define L310_AUX_CTRL_DATA_PREFETCH_MASK	(1 << 28)
 #define L310_AUX_CTRL_INST_PREFETCH_MASK	(1 << 29)
 
+#define L310_LATENCY_CTRL_SETUP(n)		((n) << 0)
+#define L310_LATENCY_CTRL_RD(n)			((n) << 4)
+#define L310_LATENCY_CTRL_WR(n)			((n) << 8)
+
 #define L2X0_CACHE_ID_PART_MASK     (0xf << 6)
 #define L2X0_CACHE_ID_PART_L310     (3 << 6)
 #define L2X0_CACHE_ID_RTL_MASK          0x3f
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index fcf211d62b..b53f22e621 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -57,19 +57,48 @@ void enable_caches(void)
 }
 
 #ifdef CONFIG_SYS_L2_PL310
+static void setup_cache_latency(void)
+{
+	const void *blob = gd->fdt_blob;
+	int node;
+	u32 latency;
+	u32 data[3];
+
+	/* find the l2-cache node */
+	node = fdt_node_offset_by_compatible(blob, -1, "arm,pl310-cache");
+
+	fdtdec_get_int_array(blob, node, "arm,tag-latency", data, 3);
+	latency = L310_LATENCY_CTRL_RD(data[0] - 1) |
+		  L310_LATENCY_CTRL_WR(data[1] - 1) |
+		  L310_LATENCY_CTRL_SETUP(data[2] - 1);
+
+	writel(latency, &pl310->pl310_tag_latency_ctrl);
+
+	fdtdec_get_int_array(blob, node, "arm,data-latency", data, 3);
+	latency = L310_LATENCY_CTRL_RD(data[0] - 1) |
+		  L310_LATENCY_CTRL_WR(data[1] - 1) |
+		  L310_LATENCY_CTRL_SETUP(data[2] - 1);
+	writel(latency, &pl310->pl310_data_latency_ctrl);
+
+	if (fdtdec_get_bool(blob, node, "arm,shared-override"))
+		setbits_le32(&pl310->pl310_aux_ctrl,
+			     L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+	if (fdtdec_get_config_int(blob, "prefetch-data", 1))
+		setbits_le32(&pl310->pl310_aux_ctrl,
+			     L310_AUX_CTRL_DATA_PREFETCH_MASK);
+
+	if (fdtdec_get_config_int(blob, "prefetch-instr", 1))
+		setbits_le32(&pl310->pl310_aux_ctrl,
+			     L310_AUX_CTRL_INST_PREFETCH_MASK);
+}
+
 void v7_outer_cache_enable(void)
 {
 	/* Disable the L2 cache */
 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 
-	writel(0x111, &pl310->pl310_tag_latency_ctrl);
-	writel(0x121, &pl310->pl310_data_latency_ctrl);
-
-	/* enable BRESP, instruction and data prefetch, full line of zeroes */
-	setbits_le32(&pl310->pl310_aux_ctrl,
-		     L310_AUX_CTRL_DATA_PREFETCH_MASK |
-		     L310_AUX_CTRL_INST_PREFETCH_MASK |
-		     L310_SHARED_ATT_OVERRIDE_ENABLE);
+	setup_cache_latency();
 
 	/* Enable the L2 cache */
 	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-- 
2.20.0