[U-Boot] [PATCH v2 1/3] fsl_sec: fix register layout on Layerscape architectures

Prabhakar Kushwaha prabhakar.kushwaha at nxp.com
Mon Mar 4 08:53:57 UTC 2019


> -----Original Message-----
> From: laurentiu.tudor at nxp.com <laurentiu.tudor at nxp.com>
> Sent: Tuesday, February 26, 2019 4:49 PM
> To: u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha at nxp.com>
> Cc: Bharat Bhushan <bharat.bhushan at nxp.com>; Horia Geanta
> <horia.geanta at nxp.com>; Laurentiu Tudor <laurentiu.tudor at nxp.com>
> Subject: [PATCH v2 1/3] fsl_sec: fix register layout on Layerscape architectures
> 
> From: Laurentiu Tudor <laurentiu.tudor at nxp.com>
> 
> On Layerscape architectures the SEC memory map is 1MB and the register
> blocks contained in it are 64KB aligned, not 4KB as the ccsr_sec structure
> currently assumes. Fix the layout of the structure for these architectures.
> 
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor at nxp.com>
> Reviewed-by: Horia Geanta <horia.geanta at nxp.com>
> Reviewed-by: Bharat Bhushan <bharat.bhushan at nxp.com>
> ---

Patch set applied to u-boot-fsl-qoriq. Awaiting upstream

--pk


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