[U-Boot] [RFC PATCHv1 3/3] ARM: socfpga: let the pl310 driver configure the cache settings

[Dinh Nguyen]

On 3/5/19 1:20 PM, Marek Vasut wrote:
> On 3/5/19 8:03 PM, Dinh Nguyen wrote:
>> Load the PL310 L2 cache driver and allow it to setup the cache settings
>>
>> Signed-off-by: Dinh Nguyen <dinguyen at kernel.org>
>> ---
>>  arch/arm/mach-socfpga/misc.c | 15 ++-------------
>>  1 file changed, 2 insertions(+), 13 deletions(-)
>>
>> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
>> index fcf211d62b..fb0cfd3c1a 100644
>> --- a/arch/arm/mach-socfpga/misc.c
>> +++ b/arch/arm/mach-socfpga/misc.c
>> @@ -59,20 +59,9 @@ void enable_caches(void)
>>  #ifdef CONFIG_SYS_L2_PL310
>>  void v7_outer_cache_enable(void)
>>  {
>> -	/* Disable the L2 cache */
>> -	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
>> -
>> -	writel(0x111, &pl310->pl310_tag_latency_ctrl);
>> -	writel(0x121, &pl310->pl310_data_latency_ctrl);
>> -
>> -	/* enable BRESP, instruction and data prefetch, full line of zeroes */
>> -	setbits_le32(&pl310->pl310_aux_ctrl,
>> -		     L310_AUX_CTRL_DATA_PREFETCH_MASK |
>> -		     L310_AUX_CTRL_INST_PREFETCH_MASK |
>> -		     L310_SHARED_ATT_OVERRIDE_ENABLE);
>> +	struct udevice *dev;
>>  
>> -	/* Enable the L2 cache */
>> -	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
>> +	uclass_first_device(UCLASS_MISC, &dev);
> 
> Error handling might help here
> 

Agreed..Just trying to solicit comments on whether this is the right
approach? Will add error handling..

Thanks for reviewing...
Dinh