[U-Boot] [PATCH v2 7/9] riscv: do not rely on hart ID passed by previous boot stage

[Anup Patel]

> -----Original Message-----
> From: Lukas Auer <lukas.auer at aisec.fraunhofer.de>
> Sent: Wednesday, March 6, 2019 4:23 AM
> To: u-boot at lists.denx.de
> Cc: Atish Patra <Atish.Patra at wdc.com>; Anup Patel
> <Anup.Patel at wdc.com>; Bin Meng <bmeng.cn at gmail.com>; Andreas
> Schwab <schwab at suse.de>; Palmer Dabbelt <palmer at sifive.com>;
> Alexander Graf <agraf at suse.de>; Lukas Auer
> <lukas.auer at aisec.fraunhofer.de>; Rick Chen <rick at andestech.com>; Anup
> Patel <anup at brainfault.org>
> Subject: [PATCH v2 7/9] riscv: do not rely on hart ID passed by previous boot
> stage
> 
> RISC-V U-Boot expects the hart ID to be passed to it via register a0 by the
> previous boot stage. Machine mode firmware such as BBL and OpenSBI do
> this when starting their payload (U-Boot) in supervisor mode. If U-Boot is
> running in machine mode, this task must be handled by the boot ROM.
> Explicitly populate register a0 with the hart ID from the mhartid CSR to avoid
> possible problems on RISC-V processors with a boot ROM that does not
> handle this task.
> 
> Suggested-by: Rick Chen <rick at andestech.com>
> Signed-off-by: Lukas Auer <lukas.auer at aisec.fraunhofer.de>
> ---
> 
> Changes in v2:
> - New patch to populate register a0 with the hart ID from the mhartid CSR in
> machine-mode
> 
>  arch/riscv/cpu/start.S | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index
> 79b753847c..d4daa6e0bf 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -36,6 +36,10 @@
>  .section .text
>  .globl _start
>  _start:
> +#ifdef CONFIG_RISCV_MMODE
> +	csrr	a0, mhartid
> +#endif
> +
>  	/* save hart id and dtb pointer */
>  	mv	s0, a0
>  	mv	s1, a1
> --
> 2.20.1

Reviewed-by: Anup Patel <anup.patel at wdc.com>

Regards,
Anup