[U-Boot] [PATCH v11 3/9] ARM: socfpga: Cleaning up the messages

[Dinh Nguyen]

On 3/5/19 10:23 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee at intel.com>
> 
> Ensure the comment and debug messages are always consistent with the rest.

The rest of what? This patch seems unnecessary to me.

Dinh

> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
> ---
>  drivers/fpga/socfpga_arria10.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
> index 114dd910ab..b0abe1955c 100644
> --- a/drivers/fpga/socfpga_arria10.c
> +++ b/drivers/fpga/socfpga_arria10.c
> @@ -94,7 +94,7 @@ int fpgamgr_wait_early_user_mode(void)
>  		i++;
>  	}
>  
> -	debug("Additional %i sync word needed\n", i);
> +	debug("FPGA: Additional %i sync word needed\n", i);
>  
>  	/* restoring original CDRATIO */
>  	fpgamgr_set_cd_ratio(cd_ratio);
> @@ -172,9 +172,10 @@ static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
>  	compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
>  	compress = !compress;
>  
> -	debug("header word %d = %08x\n", 69, rbf_data[69]);
> -	debug("header word %d = %08x\n", 229, rbf_data[229]);
> -	debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
> +	debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
> +	debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
> +	debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
> +	     compress);
>  
>  	/*
>  	 * from the register map description of cdratio in imgcfg_ctrl_02:
> @@ -455,10 +456,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
>  {
>  	int status;
>  
> -	/* disable all signals from hps peripheral controller to fpga */
> +	/* Disable all signals from hps peripheral controller to fpga */
>  	writel(0, &system_manager_base->fpgaintf_en_global);
>  
> -	/* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
> +	/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
>  	socfpga_bridges_reset();
>  
>  	/* Initialize the FPGA Manager */
>