[U-Boot] [PATCH v2 0/9] SMP support for RISC-V

[Anup Patel]

On Wed, Mar 6, 2019 at 5:17 PM Andreas Schwab <schwab at suse.de> wrote:
>
> On Mär 06 2019, Anup Patel <Anup.Patel at wdc.com> wrote:
>
> >> -----Original Message-----
> >> From: Andreas Schwab <schwab at suse.de>
> >> Sent: Wednesday, March 6, 2019 4:27 PM
> >> To: Anup Patel <Anup.Patel at wdc.com>
> >> Cc: Auer, Lukas <lukas.auer at aisec.fraunhofer.de>; u-boot at lists.denx.de;
> >> paul.walmsley at sifive.com; agraf at suse.de; anup at brainfault.org;
> >> baruch at tkos.co.il; daniel.schwierzeck at gmail.com; bmeng.cn at gmail.com;
> >> rick at andestech.com; sr at denx.de; palmer at sifive.com; Atish Patra
> >> <Atish.Patra at wdc.com>
> >> Subject: Re: [PATCH v2 0/9] SMP support for RISC-V
> >>
> >> Apparently sometimes u-boot tries to boot the kernel on heart 0 (the E51
> >> core), which will then fail to start userspace, since that cannot cope with the
> >> missing fpu.
> >
> > That's not possible
>
> Yes, it is.
>
>
> OpenSBI v0.3 (Mar  6 2019 10:55:01)
>    ____                    _____ ____ _____
>   / __ \                  / ____|  _ \_   _|
>  | |  | |_ __   ___ _ __ | (___ | |_) || |
>  | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
>  | |__| | |_) |  __/ | | |____) | |_) || |_
>   \____/| .__/ \___|_| |_|_____/|____/_____|
>         | |
>         |_|
>
> Platform Name          : SiFive Freedom U540
> Platform HART Features : RV64ACDFIMSU
> Platform Max HARTs     : 5
> Current Hart           : 2
> Firmware Base          : 0x80000000
> Firmware Size          : 88 KB
> Runtime SBI Version    : 0.1
>
> PMP0: 0x0000000080000000-0x000000008001ffff (A)
> PMP1: 0x0000000000000000-0x0000007fffffffff (A,R,W,X)
>
>
> U-Boot 2019.04-rc3-00010-g3ea5582c09 (Mar 06 2019 - 10:06:10 +0100)
>
> CPU:   rv64imac
> Model: sifive,hifive-unleashed-a00
> DRAM:  8 GiB

How does this prove that U-Boot is booting on HART 0?

This seems to be warm reset issues for which fixes from Atish are
not yet merged.

Regards,
Anup