[U-Boot] [PATCH v2 7/9] riscv: do not rely on hart ID passed by previous boot stage

[Bin Meng]

On Wed, Mar 6, 2019 at 6:54 AM Lukas Auer
<lukas.auer at aisec.fraunhofer.de> wrote:
>
> RISC-V U-Boot expects the hart ID to be passed to it via register a0 by
> the previous boot stage. Machine mode firmware such as BBL and OpenSBI
> do this when starting their payload (U-Boot) in supervisor mode. If
> U-Boot is running in machine mode, this task must be handled by the boot
> ROM. Explicitly populate register a0 with the hart ID from the mhartid
> CSR to avoid possible problems on RISC-V processors with a boot ROM that
> does not handle this task.
>
> Suggested-by: Rick Chen <rick at andestech.com>
> Signed-off-by: Lukas Auer <lukas.auer at aisec.fraunhofer.de>
> ---
>
> Changes in v2:
> - New patch to populate register a0 with the hart ID from the mhartid
> CSR in machine-mode
>
>  arch/riscv/cpu/start.S | 4 ++++
>  1 file changed, 4 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
Tested-by: Bin Meng <bmeng.cn at gmail.com>