[U-Boot] [PATCHv4 08/12] pci: ls_pcie_g4: add Workaround for A-011577

[Z.q. Hou]

From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>

PCIe configuration access to non-existent function triggered
SERROR interrupt exception.

Workaround:
Disable error reporting on AXI bus during the Vendor ID read
transactions in enumeration.

This ERRATA is only for LX2160A Rev1.0 and will be fixed in Rev2.0.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
---
V4:
 - No change

 drivers/pci/pcie_layerscape_gen4.c | 8 ++++++++
 drivers/pci/pcie_layerscape_gen4.h | 5 +++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c
index 4e0d5b168e..799da2f7df 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -242,6 +242,9 @@ static int ls_pcie_g4_read_config(struct udevice *bus, pci_dev_t bdf,
 
 	address = ls_pcie_g4_conf_address(pcie, bdf, offset);
 
+	if (pcie->rev == REV_1_0 && offset == PCI_VENDOR_ID)
+		lut_writel(pcie, 0x0 << PCIE_LUT_GCR_RRE, PCIE_LUT_GCR);
+
 	switch (size) {
 	case PCI_SIZE_8:
 		*valuep = readb(address);
@@ -257,6 +260,9 @@ static int ls_pcie_g4_read_config(struct udevice *bus, pci_dev_t bdf,
 		break;
 	}
 
+	if (pcie->rev == REV_1_0 && offset == PCI_VENDOR_ID)
+		lut_writel(pcie, 0x1 << PCIE_LUT_GCR_RRE, PCIE_LUT_GCR);
+
 	return ret;
 }
 
@@ -518,6 +524,8 @@ static int ls_pcie_g4_probe(struct udevice *dev)
 	      dev->name, (unsigned long)pcie->ccsr, (unsigned long)pcie->cfg,
 	      pcie->big_endian);
 
+	pcie->rev = readb(pcie->ccsr + PCI_REVISION_ID);
+
 	pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
 
 	if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
diff --git a/drivers/pci/pcie_layerscape_gen4.h b/drivers/pci/pcie_layerscape_gen4.h
index 356b49f9ce..137768cae7 100644
--- a/drivers/pci/pcie_layerscape_gen4.h
+++ b/drivers/pci/pcie_layerscape_gen4.h
@@ -11,6 +11,8 @@
 #include <pci.h>
 #include <dm.h>
 
+#define REV_1_0					(0x10)
+
 #ifndef CONFIG_SYS_PCI_MEMORY_SIZE
 #define CONFIG_SYS_PCI_MEMORY_SIZE		(4 * 1024 * 1024 * 1024ULL)
 #endif
@@ -161,6 +163,8 @@
 #define PCIE_LUT_LDR(n)				(0x804 + (n) * 8)
 #define PCIE_LUT_ENABLE				BIT(31)
 #define PCIE_LUT_ENTRY_COUNT			32
+#define PCIE_LUT_GCR				(0x28)
+#define PCIE_LUT_GCR_RRE			(0)
 
 /* PF control registers */
 #define PCIE_LTSSM_STA				0x7fc
@@ -190,6 +194,7 @@ struct ls_pcie_g4 {
 	int stream_id_cur;
 	int mode;
 	int sriov_support;
+	u8 rev;
 };
 
 extern struct list_head ls_pcie_g4_list;
-- 
2.17.1