[U-Boot] Custom SPL for im.X6UL

Mon Mar 11 09:43:05 UTC 2019

Hi 

> -----Original Message-----
> From: Araya, Jose [mailto:j.araya at sensopart.de]
> Sent: 2019年3月11日 16:50
> To: Peng Fan <peng.fan at nxp.com>
> Subject: AW: [U-Boot] Custom SPL for im.X6UL
> 
> Hi Peng,
> 
> thanks for answering! Just a follow up question:
> 
> Does the U-boot from NXP run in OCRAM or in DRAM?

For i.MX6UL, NXP released U-Boot runs from DRAM, no SPL.

> 
> I read that a multi-stage boot is faster and more efficient, that makes me
> think that if I use a single-stage boot it should run in OCRAM (which is limited)
> and that's why the multi-stage (which uses DRAM) is actually faster. That's
> why my question arises.

You could use the upstream uboot for i.MX6UL, it supports SPL runs from OCRAM.

Regards,
Peng.

> 
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> Thanks!
> 
> Moises
> 
> -----Ursprüngliche Nachricht-----
> Von: Peng Fan <peng.fan at nxp.com>
> Gesendet: Samstag, 9. März 2019 02:11
> An: Araya, Jose <j.araya at sensopart.de>; u-boot at lists.denx.de
> Betreff: RE: [U-Boot] Custom SPL for im.X6UL
> 
> 
> 
> > -----Original Message-----
> > From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Araya,
> > Jose
> > Sent: 2019年3月9日 0:59
> > To: u-boot at lists.denx.de
> > Subject: [U-Boot] Custom SPL for im.X6UL
> >
> > Hello everyone,
> >
> > I would like to ask what would be a good starting point to have a
> > custom multi-stage booting for the NXP i.mx6UL processor?
> >
> > Basically I need to be able to configure an FPGA before the U-Boot is
> executed.
> > The reason for that is that the PGA must be configured so that the
> > im6UL can have a physical connection to the DRAM. To clarify:
> >
> >
> > -       In the circuit, the DRAM will be multiplexed by an FPGA. If the
> FPGA
> > is not configured, the imx6UL has no access to the DRAM.
> >
> > -       The imx6UL has a direct SPI connection to the flash and to the
> FPGA,
> > so all I need is to take the bitstream from a given location in the
> > FLASH and load it into the FPGA, then just wait for a flag (GPIO?)
> > saying that the FPGA was successfully configured and keep the booting
> > process in the processor as normal.
> >
> >
> > As I haven't done yet anything similar, just wanted to know if you
> > have any recommendations regarding where to start and some  hints to
> proceed.
> 
> SPL might help here, because it runs in OCRAM.
> 
> Regards,
> Peng.
> 
> >
> > Thanks in advance!
> >
> > Bests,
> >
> > Jose Moises
> >
> >
> >
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