[U-Boot] [PATCH v2 0/9] SMP support for RISC-V
Palmer Dabbelt
palmer at sifive.com
Mon Mar 11 11:56:27 UTC 2019
On Thu, 07 Mar 2019 19:37:30 PST (-0800), Anup Patel wrote:
>
>
>> -----Original Message-----
>> From: Andreas Schwab <schwab at suse.de>
>> Sent: Thursday, March 7, 2019 2:50 PM
>> To: Anup Patel <Anup.Patel at wdc.com>
>> Cc: Atish Patra <Atish.Patra at wdc.com>; Anup Patel <anup at brainfault.org>;
>> Auer, Lukas <lukas.auer at aisec.fraunhofer.de>; paul.walmsley at sifive.com;
>> agraf at suse.de; u-boot at lists.denx.de; baruch at tkos.co.il;
>> daniel.schwierzeck at gmail.com; bmeng.cn at gmail.com;
>> rick at andestech.com; sr at denx.de; palmer at sifive.com
>> Subject: Re: [PATCH v2 0/9] SMP support for RISC-V
>>
>> On Mär 07 2019, Anup Patel <Anup.Patel at wdc.com> wrote:
>>
>> > Like I mentioned, there is no functional issue with this series. The
>> > warm-boot issues were fixed in OpenSBI.
>> >
>> > @Andreas, please try at your end.
>>
>> As long as issue#65 isn't fixed opensbi is mostly a no-go for me. At least it
>> gives me more reasons to press the reset button. :-)
>
> The reset button works fine for me an Atish. I am sure it works fine for lot of
> other folks too.
>
> BTW, as-per discussion with SiFive folks the reset button on Unleashed
> Board is not much tested and it can misbehave on certain boards. It is quite
> possible that you might have a "flaky" board.
I don't think the reset button differs between boards. As far as I know, the
issues are really just that it doesn't reset everything -- specifically some of
the IP on the chip (clock, power, JTAG) isn't reset and nothing on the board
(SD, ethernet, PCIe, etc) is reset. This frequently results in flakiness when
debugging drivers, but the cores and memory system should all be OK.
Is that issue 65 on github.com/opensbi? If so it clearly says this isn't a
reset button issue.
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