[U-Boot] [PATCH v3 00/11] SMP support for RISC-V

[Lukas Auer]

This patch series adds SMP support for RISC-V to U-Boot. It allows
U-Boot to run on multi-hart systems (hart is the RISC-V terminology for
hardware thread). Images passed to bootm will be started on all harts.
The bootm command is currently the only one that will boot images on all
harts, bootefi is not yet supported.

The patches have been successfully tested on both QEMU (machine and
supervisor mode) and the HiFive Unleashed board (supervisor mode), using
BBL and OpenSBI.
Mainline QEMU requires two patches [1, 2] to run in this configuration.
Patch [1] has been dropped and will be replaced with a U-Boot patch.

[1]: https://patchwork.ozlabs.org/patch/1039493/
[2]: https://patchwork.ozlabs.org/patch/1039082/

Changes in v3:
- Print error if riscv_send_ipi() fails
- Adjust error message for failures of riscv_clear_ipi() to match error
message for failures of riscv_send_ipi()
- New patch to save the hart ID in register tp instead of s0
- Adjust patch to use the new location of the hart ID (register tp)
- New patch to hang if relocation of secondary harts fails

Changes in v2:
- Remove unneeded quotes from NR_CPUS Kconfig entry
- Move memory barrier from send_ipi_many() to handle_ipi()
- Add check in send_ipi_many so that IPIs are only sent to available
harts as indicated by the available_harts mask
- Implement hart lottery to pick main hart to run U-Boot
- Remove CONFIG_MAIN_HART as it is not required anymore
- Register available harts in the available_harts mask
- New patch to populate register a0 with the hart ID from the mhartid
CSR in machine-mode
- New patch to enable SMP on the SiFive FU540, which was previously sent
independently

Lukas Auer (11):
  riscv: add infrastructure for calling functions on other harts
  riscv: import the supervisor binary interface header file
  riscv: implement IPI platform functions using SBI
  riscv: delay initialization of caches and debug UART
  riscv: save hart ID in register tp instead of s0
  riscv: add support for multi-hart systems
  riscv: boot images passed to bootm on all harts
  riscv: do not rely on hart ID passed by previous boot stage
  riscv: hang if relocation of secondary harts fails
  riscv: fu540: enable SMP
  riscv: qemu: enable SMP

 arch/riscv/Kconfig                   |  28 +++++
 arch/riscv/cpu/cpu.c                 |   9 +-
 arch/riscv/cpu/start.S               | 167 +++++++++++++++++++++++++--
 arch/riscv/include/asm/csr.h         |   1 +
 arch/riscv/include/asm/global_data.h |   6 +
 arch/riscv/include/asm/sbi.h         |  94 +++++++++++++++
 arch/riscv/include/asm/smp.h         |  53 +++++++++
 arch/riscv/lib/Makefile              |   2 +
 arch/riscv/lib/asm-offsets.c         |   1 +
 arch/riscv/lib/bootm.c               |  13 ++-
 arch/riscv/lib/sbi_ipi.c             |  25 ++++
 arch/riscv/lib/smp.c                 | 118 +++++++++++++++++++
 board/emulation/qemu-riscv/Kconfig   |   1 +
 board/sifive/fu540/Kconfig           |   1 +
 14 files changed, 507 insertions(+), 12 deletions(-)
 create mode 100644 arch/riscv/include/asm/sbi.h
 create mode 100644 arch/riscv/include/asm/smp.h
 create mode 100644 arch/riscv/lib/sbi_ipi.c
 create mode 100644 arch/riscv/lib/smp.c

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2.20.1