[U-Boot] [PATCH 3/3] armv8: ls1028aqds: Add support of LS1028AQDS

Bhaskar Upadhaya bhaskar.upadhaya at nxp.com
Mon Mar 18 09:45:19 UTC 2019


LS1028A Development System (QDS) is a high-performance
computing, evaluation, and development platform that supports
LS1028A QorIQ Architecture processor.

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta at nxp.com>
Signed-off-by: Rai Harninder <harninder.rai at nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya at nxp.com>
---
 arch/arm/Kconfig                    |  11 ++
 arch/arm/cpu/armv8/Kconfig          |   2 +-
 arch/arm/dts/fsl-ls1028a-qds.dts    |  16 +++
 board/freescale/ls1028a/Kconfig     |  39 +++++++
 board/freescale/ls1028a/MAINTAINERS |  10 ++
 board/freescale/ls1028a/README      |  85 +++++++++++++++
 board/freescale/ls1028a/ls1028a.c   |  89 ++++++++++++++++
 configs/ls1028aqds_tfa_defconfig    |  61 +++++++++++
 include/configs/ls1028aqds.h        | 206 ++++++++++++++++++++++++++++++++++++
 9 files changed, 518 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-ls1028a-qds.dts
 create mode 100644 configs/ls1028aqds_tfa_defconfig
 create mode 100644 include/configs/ls1028aqds.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index aaaf36a..7741ea2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1203,6 +1203,17 @@ config TARGET_LS1012AFRDM
 	  development platform that supports the QorIQ LS1012A
 	  Layerscape Architecture processor.
 
+config TARGET_LS1028AQDS
+	bool "Support ls1028aqds"
+	select ARCH_LS1028A
+	select ARM64
+	select ARMV8_MULTIENTRY
+	help
+	  Support for Freescale LS1028AQDS platform
+	  The LS1028A Development System (QDS) is a high-performance
+	  development platform that supports the QorIQ LS1028A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1028ARDB
 	bool "Support ls1028ardb"
 	select ARCH_LS1028A
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index a4fa63b..3e9d47a 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -104,7 +104,7 @@ config PSCI_RESET
 		   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
 		   !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
 		   !TARGET_LS1012AFRWY && \
-		   !TARGET_LS1028ARDB && \
+		   !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \
 		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
 		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
 		   !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts b/arch/arm/dts/fsl-ls1028a-qds.dts
new file mode 100644
index 0000000..131fbb7
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP ls1028AQDS device tree source
+ *
+ * Copyright 2018-2019 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1028a.dtsi"
+
+/ {
+	model = "NXP Layerscape 1028a QDS Board";
+	compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
+};
diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig
index f4733c2..f8c2fe8 100644
--- a/board/freescale/ls1028a/Kconfig
+++ b/board/freescale/ls1028a/Kconfig
@@ -1,3 +1,42 @@
+if TARGET_LS1028AQDS
+
+config SYS_BOARD
+	default "ls1028a"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1028aqds"
+
+config EMMC_BOOT
+	bool "Support for booting from EMMC"
+	default n
+
+config SYS_TEXT_BASE
+	default 0x96000000 if SD_BOOT || EMMC_BOOT
+	default 0x82000000 if TFABOOT
+	default 0x20100000
+
+if FSL_LS_PPA
+config SYS_LS_PPA_FW_ADDR
+	hex "PPA Firmware Addr"
+	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
+	default 0x400000 if SYS_LS_PPA_FW_IN_MMC && ARCH_LS1028A
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+	hex "PPA header Addr"
+	default 0x20600000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
+endif
+endif
+
+source "board/freescale/common/Kconfig"
+
+endif
+
 if TARGET_LS1028ARDB
 
 config SYS_BOARD
diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS
index f4990a2..8c01bbb 100644
--- a/board/freescale/ls1028a/MAINTAINERS
+++ b/board/freescale/ls1028a/MAINTAINERS
@@ -1,3 +1,13 @@
+LS1028AQDS BOARD
+M:	Sudhanshu Gupta <sudhanshu.gupta at nxp.com>
+M:	Rai Harninder <harninder.rai at nxp.com>
+M:	Rajesh Bhagat <rajesh.bhagat at nxp.com>
+S:	Maintained
+F:	board/freescale/ls1028a/
+F:	include/configs/ls1028a_common.h
+F:	include/configs/ls1028aqds.h
+F:	configs/ls1028aqds_tfa_defconfig
+
 LS1028ARDB BOARD
 M:	Sudhanshu Gupta <sudhanshu.gupta at nxp.com>
 M:	Rai Harninder <harninder.rai at nxp.com>
diff --git a/board/freescale/ls1028a/README b/board/freescale/ls1028a/README
index a3ce859..678b9b5 100644
--- a/board/freescale/ls1028a/README
+++ b/board/freescale/ls1028a/README
@@ -73,6 +73,91 @@ Serial audio interface(SAI)
    stereo speakers
  - IEEE1588 interface to support audio on SAI4
 
+QDS Default Switch Settings (1: ON; 0: OFF)
+-------------------------------------------
+For SD Boot
+SW1 : 10000000
+SW2 : 11100110
+SW3 : 00000010
+SW4 : 00000000
+SW5 : 00000000
+SW6 : 00000000
+SW7 : 11110011
+SW8 : 11100000
+SW9 : 10000001
+SW10: 11100000
+
+For FlexSPI Boot
+SW1 : 11110000
+SW2 : 00000110
+SW3 : 00000010
+SW4 : 00000000
+SW5 : 01100000
+SW6 : 01010000
+SW7 : 11110011
+SW8 : 11100000
+SW9 : 10000000
+SW10: 11100000
+
+LS1028AQDS board Overview
+-------------------------
+Processor
+ Two Arm Cortex- A72 processor cores:
+  - Based on 64-bit ARMv8 architecture
+  - Up to 1.3 GHz operation
+  - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
+    data cache
+  - Arranged as a single cluster of two cores sharing a single 1 MB L2
+    cache
+DDR memory
+ - Supports data rates of up to 1.6 GT/s for both, DDR4 and DDR3L
+ - Supports a single- or dual-ranked SODIMM or UDIMM connector
+ - 32-bit data and 4-bit ECC
+ - Supports x8/x16 devices
+ - Supports ECC error detection and correction
+ - 1.35 V or 1.2 V DDR power supply, with automatic tracking of VTT, to
+   all devices in case of DDR3L or DDR4, respectively — Power can
+   switch to 1.35 V or 1.2 V, based on the switch settings for DDR3L or
+   DDR4 devices, respectively
+SerDes (Serializer/Deserializer)
+ - Four-lane (0-3) SerDes:
+ - Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10
+   Gbit SXGMII, 1 Gbit SGMII
+ - Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
+   SGMII, 10 Gbit QXGMII, 5 Gbit QSGMII, 1 Gbit SGMII
+ - Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
+   SGMII
+ - Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
+   SGMII, SATA 2.0/3.0
+ - Four slots on SerDes lanes support PCIe Gen1/2/3, 1 Gbit SGMII
+   add-in cards
+ - Lane 1 connects to a 2x10 connector with SFP+ through a retimer;
+   lane 2 (TX lines) connects to an SMA connector
+   Lane 3 connects to 1x7 header to support SATA devices
+eSDHC
+ - eSDHC1, eSDHC2
+SPI
+ - SPI1 and SPI2 support three onboard SPI flash memory devices:
+    512 Mbit high-speed flash (with speed of up to 108/54 MHz)
+    memory for storage
+    4 Mbit low-speed flash memory (with speed of up to 40 MHz)
+    64 Mbit high-speed flash memory (with speed of up to 104/80
+    MHz)
+ - SPI3 supports one onboard 64 Mbit SPI flash memory (with speed of
+   up to 104/80 MHz)
+ - All memories operate at 1.8 V
+ - A header is provided on SPI1 to test SPI slave mode
+I2C
+ - LS1028A supports eight I2C controllers
+Serial audio interface(SAI)
+ Two SAI ports with audio codec SGTL5000:
+  - Include stereo LINEIN with support for external analog input
+  - Provide headphone and line output
+Display
+ - DisplayPort connector to connect the DP data to a 4K display device
+   (computer monitor)
+ - eDP connector to connect the DP data to a 4K display panel
+
 FlexSPI flash memory map valid for both QDS and RDB
   Image                               Flash Offset
  RCW+PBI                             0x00000000
diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c
index 63f8b7f..9d7251e 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -27,6 +27,39 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int config_board_mux(void)
+{
+#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
+	u8 reg;
+
+	reg = QIXIS_READ(brdcfg[13]);
+	/* Field| Function
+	 * --------------------------------------------------------------
+	 * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
+	 * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
+	 * --------------------------------------------------------------
+	 * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
+	 * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
+	 */
+	reg &= ~(0xf0);
+	reg |= 0xb0;
+	QIXIS_WRITE(brdcfg[13], reg);
+
+	reg = QIXIS_READ(brdcfg[15]);
+	/* Field| Function
+	 * --------------------------------------------------------------
+	 * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
+	 * CAN1 | 0= CAN #1 transceiver enabled
+	 * --------------------------------------------------------------
+	 * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
+	 * CAN2 | 0= CAN #2 transceiver enabled
+	 */
+	reg &= ~(0xc0);
+	QIXIS_WRITE(brdcfg[15], reg);
+#endif
+	return 0;
+}
+
 int board_init(void)
 {
 #ifdef CONFIG_ENV_IS_NOWHERE
@@ -55,6 +88,15 @@ int board_eth_init(bd_t *bis)
 	return pci_eth_init(bis);
 }
 
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+	config_board_mux();
+
+	return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
 #ifdef CONFIG_SYS_I2C_EARLY_INIT
@@ -195,6 +237,53 @@ int checkboard(void)
 }
 #endif
 
+#ifdef CONFIG_TARGET_LS1028AQDS
+int checkboard1(void)
+{
+#ifdef CONFIG_FSL_QIXIS
+	char buf[64];
+#ifndef CONFIG_SD_BOOT
+	u8 sw;
+#endif
+#endif
+
+	puts("Board: LS1028AQDS, boot from ");
+
+#ifdef CONFIG_FSL_QIXIS
+#ifdef CONFIG_SD_BOOT
+	puts("SD\n");
+#else
+
+	sw = QIXIS_READ(brdcfg[0]);
+
+	switch (sw) {
+	case 0x00:
+		printf("Serial NOR flash\n");
+		break;
+	case 0x20:
+		printf("Serial NAND flash\n");
+		break;
+	case 0x60:
+		printf("QSPI Emulator\n");
+		break;
+	default:
+		printf("invalid setting of SW: 0x%x\n", sw);
+		break;
+	}
+#endif
+
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
+	       QIXIS_READ(id), QIXIS_READ(arch));
+
+	printf("FPGA:  v%d (%s), build %d\n",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+#endif
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_TARGET_LS1028ARDB
 int checkboard1(void)
 {
diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
new file mode 100644
index 0000000..2a592a0
--- /dev/null
+++ b/configs/ls1028aqds_tfa_defconfig
@@ -0,0 +1,61 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1028AQDS=y
+CONFIG_SYS_FSL_SDHC_CLK_DIV=1
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32 at 60 cma=256M"
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h
new file mode 100644
index 0000000..6e8862f
--- /dev/null
+++ b/include/configs/ls1028aqds.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __LS1028A_QDS_H
+#define __LS1028A_QDS_H
+
+#include "ls1028a_common.h"
+
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)
+
+/* DDR */
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CONFIG_DIMM_SLOTS_PER_CTLR		2
+#define CONFIG_SYS_SDRAM_SIZE		0x80000000
+
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define QIXIS_BASE			0x7fb00000
+#define QIXIS_BASE_PHYS			QIXIS_BASE
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_LBMAP_SWITCH		1
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		5
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_SD			0x00
+#define QIXIS_LBMAP_EMMC		0x00
+#define QIXIS_LBMAP_QSPI		0x00
+#define QIXIS_RCW_SRC_SD		0x8
+#define QIXIS_RCW_SRC_EMMC		0x9
+#define QIXIS_RCW_SRC_QSPI		0xf
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+					CSPR_PORT_SIZE_8 | \
+					CSPR_MSEL_GPCM | \
+					CSPR_V)
+#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_NOR_MODE_AVD_NOR | \
+					CSOR_NOR_TRHZ_80)
+
+/*
+ * QIXIS Timing parameters for IFC GPCM
+ */
+#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xc) | \
+					FTIM0_GPCM_TEADC(0x20) | \
+					FTIM0_GPCM_TEAHC(0x10))
+#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0x50) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0x8) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0xf0))
+#define CONFIG_SYS_FPGA_FTIM3		0x0
+#endif
+
+/* RTC */
+#define CONFIG_SYS_RTC_BUS_NUM         1
+#define I2C_MUX_CH_RTC                 0xB
+
+/* FlexSPI */
+#ifdef CONFIG_NXP_FSPI
+#define NXP_FSPI_FLASH_SIZE            SZ_256M
+#define NXP_FSPI_FLASH_NUM              1
+#endif
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_SIZE			0x2000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#endif
+
+/* SATA */
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA1			AHCI_BASE_ADDR1
+#ifndef CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT2
+#endif
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+/* DSPI */
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifndef SPL_NO_ENV
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"board=ls1028aqds\0"			\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x00f00000\0"                 \
+	"kernel_addr=0x01000000\0"              \
+	"scriptaddr=0x80000000\0"               \
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"         \
+	"kernelheader_addr_r=0x80200000\0"      \
+	"load_addr=0xa0000000\0"            \
+	"kernel_addr_r=0x81000000\0"            \
+	"fdt_addr_r=0x90000000\0"               \
+	"ramdisk_addr_r=0xa0000000\0"           \
+	"kernel_start=0x1000000\0"		\
+	"kernelheader_start=0x800000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"kernel_addr_sd=0x8000\0"		\
+	"kernel_size_sd=0x14000\0"		\
+	"kernelhdr_addr_sd=0x4000\0"		\
+	"kernelhdr_size_sd=0x10\0"		\
+	"console=ttyS0,115200\0"                \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"	\
+	BOOTENV					\
+	"boot_scripts=ls1028aqds_boot.scr\0"    \
+	"boot_script_hdr=hdr_ls1028aqds_bs.out\0"	\
+	"scan_dev_for_boot_part="               \
+		"part list ${devtype} ${devnum} devplist; "   \
+		"env exists devplist || setenv devplist 1; "  \
+		"for distro_bootpart in ${devplist}; do "     \
+		  "if fstype ${devtype} "                  \
+			"${devnum}:${distro_bootpart} "      \
+			"bootfstype; then "                  \
+			"run scan_dev_for_boot; "            \
+		  "fi; "                                   \
+		"done\0"                                   \
+	"scan_dev_for_boot="				  \
+		"echo Scanning ${devtype} "		  \
+				"${devnum}:${distro_bootpart}...; "  \
+		"for prefix in ${boot_prefixes}; do "	  \
+			"run scan_dev_for_scripts; "	  \
+		"done;"					  \
+		"\0"					  \
+	"boot_a_script="				  \
+		"load ${devtype} ${devnum}:${distro_bootpart} "  \
+			"${scriptaddr} ${prefix}${script}; "    \
+		"env exists secureboot && load ${devtype} "     \
+			"${devnum}:${distro_bootpart} "		\
+			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
+			"&& esbc_validate ${scripthdraddr};"    \
+		"source ${scriptaddr}\0"	  \
+	"qspi_bootcmd=echo Trying load from flexspi..;"      \
+		"sf probe && sf read $load_addr "         \
+		"$kernel_start $kernel_size; env exists secureboot "	\
+		"&& sf read $kernelheader_addr_r $kernelheader_start "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+		"bootm $load_addr#$board\0"		\
+	"qspi_hdploadcmd=echo Trying load HDP firmware from flexspi..;"      \
+		"hdp load 0x20900000 0x2000\0"		\
+	"sd_bootcmd=echo Trying load from SD ..;"	\
+		"mmcinfo; mmc read $load_addr "		\
+		"$kernel_addr_sd $kernel_size_sd && "	\
+		"env exists secureboot && mmc read $kernelheader_addr_r " \
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$board\0"		\
+	"sd_hdploadcmd=echo Trying load HDP firmware from SD..;"      \
+		"mmcinfo;mmc read $load_addr 0x4800 0x200 "		\
+		"&& hdp load $load_addr 0x2000\0"	\
+	"emmc_bootcmd=echo Trying load from EMMC ..;"	\
+		"mmcinfo; mmc dev 1; mmc read $load_addr "		\
+		"$kernel_addr_sd $kernel_size_sd && "	\
+		"env exists secureboot && mmc read $kernelheader_addr_r " \
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$board\0"			\
+	"emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;"      \
+		"mmc dev 1;mmcinfo;mmc read $load_addr 0x4800 0x200 "		\
+		"&& hdp load $load_addr 0x2000\0"
+#endif
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+#endif /* __LS1028A_QDS_H */
-- 
1.9.1



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