[U-Boot] [PATCH 3/9] riscv: Add a SYSCON driver for Andestech's PLMT
Rick Chen
rickchen36 at gmail.com
Thu Mar 21 08:41:32 UTC 2019
Hi Bin
Bin Meng <bmeng.cn at gmail.com> 於 2019年3月20日 週三 下午3:22寫道:
>
> Hi Rick,
>
> On Tue, Mar 19, 2019 at 5:12 PM Andes <uboot at andestech.com> wrote:
> >
> > From: Rick Chen <rick at andestech.com>
> >
> > The platform-Level Machine Timer(PLMT) block
> > holds memory-mapped mtime register associated
> > with timer tick.
> >
> > This driver implements the riscv_get_time()which
>
> nits: need one space before "which"
OK
>
> > are required by the generic RISC-V timer driver.
>
> are -> is
OK
>
> >
> > Signed-off-by: Rick Chen <rick at andestech.com>
> > Cc: Greentime Hu <greentime at andestech.com>
> > ---
> > arch/riscv/Kconfig | 9 ++++++
> > arch/riscv/include/asm/global_data.h | 3 ++
> > arch/riscv/include/asm/syscon.h | 1 +
> > arch/riscv/lib/Makefile | 1 +
> > arch/riscv/lib/nds_plmt.c | 53 ++++++++++++++++++++++++++++++++++++
> > 5 files changed, 67 insertions(+)
> > create mode 100644 arch/riscv/lib/nds_plmt.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index fef11dd..697892e 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -118,6 +118,15 @@ config NDS_PLIC
> > The Andes PLIC block holds memory-mapped claim and pending registers
> > associated with software interrupt.
> >
> > +config NDS_PLMT
>
> ANDES_PLMT?
OK
>
> > + bool
> > + depends on RISCV_MMODE
> > + select REGMAP
> > + select SYSCON
> > + help
> > + The Andes PLMT block holds memory-mapped mtime register
> > + associated with timer tick.
> > +
> > config RISCV_RDTIME
> > bool
> > default y if RISCV_SMODE
> > diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
> > index 15867f5..0695ae3 100644
> > --- a/arch/riscv/include/asm/global_data.h
> > +++ b/arch/riscv/include/asm/global_data.h
> > @@ -21,6 +21,9 @@ struct arch_global_data {
> > #ifdef CONFIG_NDS_PLIC
> > void __iomem *plic; /* plic base address */
> > #endif
> > +#ifdef CONFIG_NDS_PLMT
> > + void __iomem *plmt; /* plmt base address */
> > +#endif
> > #ifdef CONFIG_SMP
> > struct ipi_data ipi[CONFIG_NR_CPUS];
> > #endif
> > diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
> > index 0229989..9fdee09 100644
> > --- a/arch/riscv/include/asm/syscon.h
> > +++ b/arch/riscv/include/asm/syscon.h
> > @@ -14,6 +14,7 @@ enum {
> > RISCV_NONE,
> > RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
> > RISCV_SYSCON_PLIC, /* Platform Level Interrup Controller (PLIC) */
> > + RISCV_SYSCON_PLMT, /* Platform Level Machine Timer (PLMT) */
> > };
> >
> > #endif /* _ASM_SYSCON_H */
> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > index 8187c2b..383eed3 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -12,6 +12,7 @@ obj-y += cache.o
> > obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> > obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> > obj-$(CONFIG_NDS_PLIC) += nds_plic.o
> > +obj-$(CONFIG_NDS_PLMT) += nds_plmt.o
> > obj-y += interrupts.o
> > obj-y += reset.o
> > obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> > diff --git a/arch/riscv/lib/nds_plmt.c b/arch/riscv/lib/nds_plmt.c
> > new file mode 100644
> > index 0000000..12d7e0e
> > --- /dev/null
> > +++ b/arch/riscv/lib/nds_plmt.c
> > @@ -0,0 +1,53 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2019, Rick Chen <rick at andestech.com>
> > + *
> > + * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
> > + * The PLMT block holds memory-mapped mtime register
> > + * associated with timer tick.
> > + */
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <regmap.h>
> > +#include <syscon.h>
> > +#include <asm/io.h>
> > +#include <asm/syscon.h>
> > +
> > +/* mtime register */
> > +#define MTIME_REG(base) ((ulong)(base))
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#define PLMT_BASE_GET(void) \
> > + do { \
> > + long *ret; \
> > + \
> > + if (!gd->arch.plmt) { \
> > + ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
> > + if (IS_ERR(ret)) \
> > + return PTR_ERR(ret); \
> > + gd->arch.plmt = ret; \
> > + } \
> > + } while (0)
> > +
> > +int riscv_get_time(u64 *time)
> > +{
> > + PLMT_BASE_GET();
> > +
> > + *time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
> > +
> > + return 0;
> > +}
> > +
> > +static const struct udevice_id nds_plmt_ids[] = {
> > + { .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },
> > + { }
> > +};
> > +
> > +U_BOOT_DRIVER(nds_plmt) = {
> > + .name = "nds_plmt",
> > + .id = UCLASS_SYSCON,
> > + .of_match = nds_plmt_ids,
> > + .flags = DM_FLAG_PRE_RELOC,
> > +};
> > --
>
> Regards,
> Bin
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