[U-Boot] [PATCH 7/9] riscv: ax25: Andes specific cache shall only support in M-mode.

[Rick Chen]

Hi Bin

Bin Meng <bmeng.cn at gmail.com> 於 2019年3月20日 週三 下午3:22寫道：
>
> Hi Rick,
>
> On Tue, Mar 19, 2019 at 5:12 PM Andes <uboot at andestech.com> wrote:
> >
> > From: Rick Chen <rick at andestech.com>
> >
>
> nits: remove the ending period in the commit title

OK
I will remove it.

Thanks for review.
Rick

>
> > Limit the cache configuration only can be supported in M mode.
> > It can not be manipulated in S mode.
> >
> > Signed-off-by: Rick Chen <rick at andestech.com>
> > Cc: Greentime Hu <greentime at andestech.com>
> > ---
> >  arch/riscv/cpu/ax25/Kconfig | 1 +
> >  1 file changed, 1 insertion(+)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
>
> Regards,
> Bin