[U-Boot] [PATCH 2/2] armv8: ls1088a: add icid setup for platform devices

[Laurentiu Tudor]

On 21.03.2019 17:10, Horia Geanta wrote:
> On 3/21/2019 2:42 PM, Tudor Laurentiu-B10716 wrote:
>> Hi Horia,
>>
>> On 21.03.2019 12:36, Horia Geanta wrote:
>>> On 3/20/2019 4:31 PM, laurentiu.tudor at nxp.com wrote:
>>>>    #define SET_SEC_QI_ICID(streamid) \
>>>> -	SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
>>>> +	SET_ICID_ENTRY("fsl,sec-v4.0", SEC_ICID_REG_VAL(streamid), \
>>> Is this a fix for LS104x? Then it should be a separate patch.
>>
>> Not really. I added an intermediate macro, SEC_ICID_REG_VAL(streamid)
>> that forms the correct register value starting from ICID, depending on
>> the chip version (the register layouts are different between the two).
>>
> This is the define
> #define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
> 
> Thus the QI ICID for LS104x changes.

Ah, alright. Good point. I checked in the manuals and this unintended 
change does indeed fix this register setup. I'm leaning towards 
mentioning this collateral fix in the commit message.

>>>> +#else /* CONFIG_FSL_LSCH2 */
>>> [...]
>>>> +#define SEC_ICID_REG_VAL(streamid) ((streamid) << 24)
>>> ICID is in lower 6:0 bits, not in 31:24.
>>
>> That was also my initial impression but it didn't work (smmu global
>> faults with icid 0). Probably there's an ambiguity related to endianness
>> in the documentation.
>>
> Note that on DPAA 2.x both the core and device (CAAM) are little endian.
> Probably the problem is with the I/O accessors writing the CAAM registers.
> 
> Instead of out_be32() use either sec_out32() (but this means splitting
> CAAM-specific code) or out_le32().
> 
> CAAM endianness can be detected using CONFIG_SYS_FSL_SEC_LE / CONFIG_SYS_FSL_SEC_BE.
> 

Thanks for the explanation. I think I can change the macros to take into 
consideration the CONFIG_*s you pointed.

---
Best Regards, Laurentiu