[U-Boot] [RFC PATCH 1/2] arch: armv8: Provide a way to disable cache maintenance ops

[Vignesh Raghavendra]

On AM654 SoC(arm64) which is IO coherent and has L3 Cache, cache
maintenance operations being done to support non-coherent platforms
causes issues.

For example, here is how U-Boot prepares/handles a buffer to receive
data from a device (DMA Write). This may vary slightly depending on the
driver framework:

	Start DMA to write to destination buffer
	Wait for DMA to be done (dma_receive()/dma_memcpy())
	Invalidate destination buffer (invalidate_dcache_range())
	Read from destination buffer

The invalidate after the DMA is needed in order to read latest data from
memory that’s updated by DMA write. Also, in case random prefetch has
pulled in buffer data during the “wait for DMA” before the DMA has
written to it. This works well for non-coherent architectures.

In case of coherent architecture with L3 cache, DMA write would directly
update L3 cache contents (assuming cacheline is present in L3) without
updating the DDR memory. So invalidate after “wait for DMA” in above
sequence would discard latest data and read will cause stale data to be
fetched from DDR. Therefore invalidate after “wait for DMA” is not
always correct on coherent architecture.

Therefore, provide a Kconfig option to disable cache maintenance ops on
coherent architectures. This has added benefit of improving the
performance of DMA transfers as we no longer need to invalidate/flush
individual cache lines(especially for buffer thats several KBs in size).

In order to facilitate use of same Kconfig across different
architecture, I have added the symbol to top level arch/Kconfig file.
Patch currently disables cache maintenance ops for arm64 only.

Signed-off-by: Vignesh Raghavendra <vigneshr at ti.com>
---
 arch/Kconfig                  |  7 +++++++
 arch/arm/cpu/armv8/cache_v8.c | 18 ++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/arch/Kconfig b/arch/Kconfig
index 2f3d07c13a18..d32a458deedc 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -227,6 +227,13 @@ config SYS_CONFIG_NAME
 	  The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
 	  should be included from include/config.h.
 
+config SYS_ARCH_IS_COHERENT
+	bool
+	help
+	Select this option, if your architecture is coherent and needs
+	to avoid cache maintenance operations. Note that, its up to the
+	individual architectures to implement this functionality
+
 source "arch/arc/Kconfig"
 source "arch/arm/Kconfig"
 source "arch/m68k/Kconfig"
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 038405173eb1..b39d6a65cf9c 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -417,6 +417,7 @@ __weak void mmu_setup(void)
 	set_sctlr(get_sctlr() | CR_M);
 }
 
+#ifndef CONFIG_SYS_ARCH_IS_COHERENT
 /*
  * Performs a invalidation of the entire data cache at all levels
  */
@@ -458,6 +459,23 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 {
 	__asm_flush_dcache_range(start, stop);
 }
+#else
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+#endif /* CONFIG_SYS_ARCH_IS_COHERENT */
 
 void dcache_enable(void)
 {
-- 
2.21.0