[U-Boot] [PATCH v2 10/10] rockchip: rk3399: add board_debug_uart_init()

[Jack Mitchell]

On 29/03/2019 01:09, Kever Yang wrote:
> Use board_debug_uart_init() for UART iomux init instead of
> do it in board_init_f, and move the function to soc file so
> that we can find all the soc/board setting in soc file and
> use a common board file for all rockchip SoCs later.
> 
> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/rk3399-board-spl.c | 50 +----------------------
>  arch/arm/mach-rockchip/rk3399/rk3399.c    | 50 +++++++++++++++++++++++
>  2 files changed, 51 insertions(+), 49 deletions(-)
> 
> diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
> index 54a4b848a3..800ca80022 100644
> --- a/arch/arm/mach-rockchip/rk3399-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
> @@ -127,53 +127,6 @@ void secure_timer_init(void)
>  	writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
>  }
>  
> -void board_debug_uart_init(void)
> -{
> -#define GRF_BASE	0xff770000
> -#define GPIO0_BASE	0xff720000
> -#define PMUGRF_BASE	0xff320000
> -	struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
> -#ifdef CONFIG_TARGET_CHROMEBOOK_BOB
> -	struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
> -	struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
> -#endif
> -
> -#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
> -	/* Enable early UART0 on the RK3399 */
> -	rk_clrsetreg(&grf->gpio2c_iomux,
> -		     GRF_GPIO2C0_SEL_MASK,
> -		     GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
> -	rk_clrsetreg(&grf->gpio2c_iomux,
> -		     GRF_GPIO2C1_SEL_MASK,
> -		     GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
> -#else
> -# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
> -	rk_setreg(&grf->io_vsel, 1 << 0);
> -
> -	/*
> -	 * Let's enable these power rails here, we are already running the SPI
> -	 * Flash based code.
> -	 */
> -	spl_gpio_output(gpio, GPIO(BANK_B, 2), 1);  /* PP1500_EN */
> -	spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
> -
> -	spl_gpio_output(gpio, GPIO(BANK_B, 4), 1);  /* PP3000_EN */
> -	spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
> -#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
> -
> -	/* Enable early UART2 channel C on the RK3399 */
> -	rk_clrsetreg(&grf->gpio4c_iomux,
> -		     GRF_GPIO4C3_SEL_MASK,
> -		     GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
> -	rk_clrsetreg(&grf->gpio4c_iomux,
> -		     GRF_GPIO4C4_SEL_MASK,
> -		     GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
> -	/* Set channel C as UART2 input */
> -	rk_clrsetreg(&grf->soc_con7,
> -		     GRF_UART_DBG_SEL_MASK,
> -		     GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
> -#endif
> -}
>  
>  void board_init_f(ulong dummy)
>  {
> @@ -183,8 +136,7 @@ void board_init_f(ulong dummy)
>  	struct rk3399_grf_regs *grf;
>  	int ret;
>  
> -#define EARLY_UART
> -#ifdef EARLY_UART
> +#ifdef CONFIG_DEBUG_UART
>  	debug_uart_init();
>  
>  # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
> diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
> index b76ba4ed32..238f79a216 100644
> --- a/arch/arm/mach-rockchip/rk3399/rk3399.c
> +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
> @@ -57,3 +57,53 @@ int arch_cpu_init(void)
>  
>  	return 0;
>  }
> +
> +#ifdef CONFIG_DEBUG_UART_BOARD_INIT
> +void board_debug_uart_init(void)
> +{
> +#define GRF_BASE	0xff770000
> +#define GPIO0_BASE	0xff720000
> +#define PMUGRF_BASE	0xff320000
> +	struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
> +#ifdef CONFIG_TARGET_CHROMEBOOK_BOB
> +	struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
> +	struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
> +#endif
> +
> +#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
> +	/* Enable early UART0 on the RK3399 */
> +	rk_clrsetreg(&grf->gpio2c_iomux,
> +		     GRF_GPIO2C0_SEL_MASK,
> +		     GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
> +	rk_clrsetreg(&grf->gpio2c_iomux,
> +		     GRF_GPIO2C1_SEL_MASK,
> +		     GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
> +#else
> +# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
> +	rk_setreg(&grf->io_vsel, 1 << 0);
> +
> +	/*
> +	 * Let's enable these power rails here, we are already running the SPI
> +	 * Flash based code.
> +	 */
> +	spl_gpio_output(gpio, GPIO(BANK_B, 2), 1);  /* PP1500_EN */
> +	spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
> +
> +	spl_gpio_output(gpio, GPIO(BANK_B, 4), 1);  /* PP3000_EN */
> +	spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
> +#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */

I understand that it's just moving the whole function over, but if I
understand correctly these are unrelated to the debug_uart_init that the
commit mentions.

> +
> +	/* Enable early UART2 channel C on the RK3399 */
> +	rk_clrsetreg(&grf->gpio4c_iomux,
> +		     GRF_GPIO4C3_SEL_MASK,
> +		     GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
> +	rk_clrsetreg(&grf->gpio4c_iomux,
> +		     GRF_GPIO4C4_SEL_MASK,
> +		     GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
> +	/* Set channel C as UART2 input */
> +	rk_clrsetreg(&grf->soc_con7,
> +		     GRF_UART_DBG_SEL_MASK,
> +		     GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
> +#endif
> +}
> +#endif
>