[U-Boot] [PATCH 3/3] net: mscc: ocelot: Update DTS for Luton pcb90

Horatiu Vultur horatiu.vultur at microchip.com
Wed May 1 11:17:00 UTC 2019


Update device tree for luton to add support for luton pcb90.
This pcb has 24 ports from which 12 ports are connected to
SerDes6G.

Signed-off-by: Horatiu Vultur <horatiu.vultur at microchip.com>
---
 arch/mips/dts/luton_pcb090.dts        | 228 +++++++++++++++++++++++++++-------
 arch/mips/dts/luton_pcb091.dts        | 132 +++++++++++++-------
 arch/mips/dts/mscc,luton.dtsi         | 126 +++----------------
 include/dt-bindings/mscc/luton_data.h |  17 +++
 4 files changed, 307 insertions(+), 196 deletions(-)
 create mode 100644 include/dt-bindings/mscc/luton_data.h

diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts
index fe457ba..ea3e3b7 100644
--- a/arch/mips/dts/luton_pcb090.dts
+++ b/arch/mips/dts/luton_pcb090.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 #include "mscc,luton.dtsi"
+#include <dt-bindings/mscc/luton_data.h>
 
 / {
 	model = "Luton26 PCB090 Reference Board";
@@ -57,52 +58,195 @@
 
 &mdio0 {
 	status = "okay";
-};
-
-&port0 {
-	phy-handle = <&phy0>;
-};
-
-&port1 {
-	phy-handle = <&phy1>;
-};
-
-&port2 {
-	phy-handle = <&phy2>;
-};
-
-&port3 {
-	phy-handle = <&phy3>;
-};
-
-&port4 {
-	phy-handle = <&phy4>;
-};
-
-&port5 {
-	phy-handle = <&phy5>;
-};
-
-&port6 {
-	phy-handle = <&phy6>;
-};
-
-&port7 {
-	phy-handle = <&phy7>;
-};
 
-&port8 {
-	phy-handle = <&phy8>;
+	phy0: ethernet-phy at 0 {
+		reg = <0>;
+	};
+	phy1: ethernet-phy at 1 {
+		reg = <1>;
+	};
+	phy2: ethernet-phy at 2 {
+		reg = <2>;
+	};
+	phy3: ethernet-phy at 3 {
+		reg = <3>;
+	};
+	phy4: ethernet-phy at 4 {
+		reg = <4>;
+	};
+	phy5: ethernet-phy at 5 {
+		reg = <5>;
+	};
+	phy6: ethernet-phy at 6 {
+		reg = <6>;
+	};
+	phy7: ethernet-phy at 7 {
+		reg = <7>;
+	};
+	phy8: ethernet-phy at 8 {
+		reg = <8>;
+	};
+	phy9: ethernet-phy at 9 {
+		reg = <9>;
+	};
+	phy10: ethernet-phy at 10 {
+		reg = <10>;
+	};
+	phy11: ethernet-phy at 11 {
+		reg = <11>;
+	};
 };
 
-&port9 {
-	phy-handle = <&phy9>;
-};
+&mdio1 {
+	status = "okay";
 
-&port10 {
-	phy-handle = <&phy10>;
+	phy12: ethernet-phy at 12 {
+		reg = <0>;
+	};
+	phy13: ethernet-phy at 13 {
+		reg = <1>;
+	};
+	phy14: ethernet-phy at 14 {
+		reg = <2>;
+	};
+	phy15: ethernet-phy at 15 {
+		reg = <3>;
+	};
+	phy16: ethernet-phy at 16 {
+		reg = <4>;
+	};
+	phy17: ethernet-phy at 17 {
+		reg = <5>;
+	};
+	phy18: ethernet-phy at 18 {
+		reg = <6>;
+	};
+	phy19: ethernet-phy at 19 {
+		reg = <7>;
+	};
+	phy20: ethernet-phy at 20 {
+		reg = <8>;
+	};
+	phy21: ethernet-phy at 21 {
+		reg = <9>;
+	};
+	phy22: ethernet-phy at 22 {
+		reg = <10>;
+	};
+	phy23: ethernet-phy at 23 {
+		reg = <11>;
+	};
 };
 
-&port11 {
-	phy-handle = <&phy11>;
+&switch {
+	ethernet-ports {
+		port0: port at 0 {
+			reg = <0>;
+			phy-handle = <&phy0>;
+		};
+		port1: port at 1 {
+			reg = <1>;
+			phy-handle = <&phy1>;
+		};
+		port2: port at 2 {
+			reg = <2>;
+			phy-handle = <&phy2>;
+		};
+		port3: port at 3 {
+			reg = <3>;
+			phy-handle = <&phy3>;
+		};
+		port4: port at 4 {
+			reg = <4>;
+			phy-handle = <&phy4>;
+		};
+		port5: port at 5 {
+			reg = <5>;
+			phy-handle = <&phy5>;
+		};
+		port6: port at 6 {
+			reg = <6>;
+			phy-handle = <&phy6>;
+		};
+		port7: port at 7 {
+			reg = <7>;
+			phy-handle = <&phy7>;
+		};
+		port8: port at 8 {
+			reg = <8>;
+			phy-handle = <&phy8>;
+		};
+		port9: port at 9 {
+			reg = <9>;
+			phy-handle = <&phy9>;
+		};
+		port10: port at 10 {
+			reg = <10>;
+			phy-handle = <&phy10>;
+		};
+		port11: port at 11 {
+			reg = <11>;
+			phy-handle = <&phy11>;
+		};
+		port12: port at 12 {
+			reg = <12>;
+			phy-handle = <&phy12>;
+			phys = <&serdes_hsio 12 SERDES6G(1) PHY_MODE_QSGMII>;
+		};
+		port13: port at 13 {
+			reg = <13>;
+			phy-handle = <&phy13>;
+			phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>;
+		};
+		port14: port at 14 {
+			reg = <14>;
+			phy-handle = <&phy14>;
+			phys = <&serdes_hsio 14 0xff PHY_MODE_QSGMII>;
+		};
+		port15: port at 15 {
+			reg = <15>;
+			phy-handle = <&phy15>;
+			phys = <&serdes_hsio 15 0xff PHY_MODE_QSGMII>;
+		};
+		port16: port at 16 {
+			reg = <16>;
+			phy-handle = <&phy16>;
+			phys = <&serdes_hsio 16 SERDES6G(2) PHY_MODE_QSGMII>;
+		};
+		port17: port at 17 {
+			reg = <17>;
+			phy-handle = <&phy17>;
+			phys = <&serdes_hsio 17 0xff PHY_MODE_QSGMII>;
+		};
+		port18: port at 18 {
+			reg = <18>;
+			phy-handle = <&phy18>;
+			phys = <&serdes_hsio 18 0xff PHY_MODE_QSGMII>;
+		};
+		port19: port at 19 {
+			reg = <19>;
+			phy-handle = <&phy19>;
+			phys = <&serdes_hsio 19 0xff PHY_MODE_QSGMII>;
+		};
+		port20: port at 20 {
+			reg = <20>;
+			phy-handle = <&phy20>;
+			phys = <&serdes_hsio 20 SERDES6G(3) PHY_MODE_QSGMII>;
+		};
+		port21: port at 21 {
+			reg = <21>;
+			phy-handle = <&phy21>;
+			phys = <&serdes_hsio 21 0xff PHY_MODE_QSGMII>;
+		};
+		port22: port at 22 {
+			reg = <22>;
+			phy-handle = <&phy22>;
+			phys = <&serdes_hsio 22 0xff PHY_MODE_QSGMII>;
+		};
+		port23: port at 23 {
+			reg = <23>;
+			phy-handle = <&phy23>;
+			phys = <&serdes_hsio 23 0xff PHY_MODE_QSGMII>;
+		};
+	};
 };
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
index f684cc8..cb78c57 100644
--- a/arch/mips/dts/luton_pcb091.dts
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -63,52 +63,94 @@
 
 &mdio0 {
 	status = "okay";
-};
-
-&port0 {
-	phy-handle = <&phy0>;
-};
-
-&port1 {
-	phy-handle = <&phy1>;
-};
-
-&port2 {
-	phy-handle = <&phy2>;
-};
-
-&port3 {
-	phy-handle = <&phy3>;
-};
 
-&port4 {
-	phy-handle = <&phy4>;
-};
-
-&port5 {
-	phy-handle = <&phy5>;
-};
-
-&port6 {
-	phy-handle = <&phy6>;
-};
-
-&port7 {
-	phy-handle = <&phy7>;
-};
-
-&port8 {
-	phy-handle = <&phy8>;
-};
-
-&port9 {
-	phy-handle = <&phy9>;
-};
-
-&port10 {
-	phy-handle = <&phy10>;
+	phy0: ethernet-phy at 0 {
+		reg = <0>;
+	};
+	phy1: ethernet-phy at 1 {
+		reg = <1>;
+	};
+	phy2: ethernet-phy at 2 {
+		reg = <2>;
+	};
+	phy3: ethernet-phy at 3 {
+		reg = <3>;
+	};
+	phy4: ethernet-phy at 4 {
+		reg = <4>;
+	};
+	phy5: ethernet-phy at 5 {
+		reg = <5>;
+	};
+	phy6: ethernet-phy at 6 {
+		reg = <6>;
+	};
+	phy7: ethernet-phy at 7 {
+		reg = <7>;
+	};
+	phy8: ethernet-phy at 8 {
+		reg = <8>;
+	};
+	phy9: ethernet-phy at 9 {
+		reg = <9>;
+	};
+	phy10: ethernet-phy at 10 {
+		reg = <10>;
+	};
+	phy11: ethernet-phy at 11 {
+		reg = <11>;
+	};
 };
 
-&port11 {
-	phy-handle = <&phy11>;
+&switch {
+	ethernet-ports {
+		port0: port at 0 {
+			reg = <0>;
+			phy-handle = <&phy0>;
+		};
+		port1: port at 1 {
+			reg = <1>;
+			phy-handle = <&phy1>;
+		};
+		port2: port at 2 {
+			reg = <2>;
+			phy-handle = <&phy2>;
+		};
+		port3: port at 3 {
+			reg = <3>;
+			phy-handle = <&phy3>;
+		};
+		port4: port at 4 {
+			reg = <4>;
+			phy-handle = <&phy4>;
+		};
+		port5: port at 5 {
+			reg = <5>;
+			phy-handle = <&phy5>;
+		};
+		port6: port at 6 {
+			reg = <6>;
+			phy-handle = <&phy6>;
+		};
+		port7: port at 7 {
+			reg = <7>;
+			phy-handle = <&phy7>;
+		};
+		port8: port at 8 {
+			reg = <8>;
+			phy-handle = <&phy8>;
+		};
+		port9: port at 9 {
+			reg = <9>;
+			phy-handle = <&phy9>;
+		};
+		port10: port at 10 {
+			reg = <10>;
+			phy-handle = <&phy10>;
+		};
+		port11: port at 11 {
+			reg = <11>;
+			phy-handle = <&phy11>;
+		};
+	};
 };
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
index de354fe..c823101 100644
--- a/arch/mips/dts/mscc,luton.dtsi
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -124,7 +124,7 @@
 			      <0x030000 0x1000>, // VTSS_TO_REW
 			      <0x070000 0x1000>, // VTSS_TO_DEVCPU_GCB
 			      <0x080000 0x0100>, // VTSS_TO_DEVCPU_QS
-			      <0x0a0000 0x0100>; // VTSS_TO_HSIO
+			      <0x0a0000 0x10000>; // VTSS_TO_HSIO
 			reg-names = "port0", "port1", "port2", "port3",
 				    "port4", "port5", "port6", "port7",
 				    "port8", "port9", "port10", "port11",
@@ -137,79 +137,6 @@
 			ethernet-ports {
 				#address-cells = <1>;
 				#size-cells = <0>;
-
-				port0: port at 0 {
-					reg = <0>;
-				};
-				port1: port at 1 {
-					reg = <1>;
-				};
-				port2: port at 2 {
-					reg = <2>;
-				};
-				port3: port at 3 {
-					reg = <3>;
-				};
-				port4: port at 4 {
-					reg = <4>;
-				};
-				port5: port at 5 {
-					reg = <5>;
-				};
-				port6: port at 6 {
-					reg = <6>;
-				};
-				port7: port at 7 {
-					reg = <7>;
-				};
-				port8: port at 8 {
-					reg = <8>;
-				};
-				port9: port at 9 {
-					reg = <9>;
-				};
-				port10: port at 10 {
-					reg = <10>;
-				};
-				port11: port at 11 {
-					reg = <11>;
-				};
-				port12: port at 12 {
-					reg = <12>;
-				};
-				port13: port at 13 {
-					reg = <13>;
-				};
-				port14: port at 14 {
-					reg = <14>;
-				};
-				port15: port at 15 {
-					reg = <15>;
-				};
-				port16: port at 16 {
-					reg = <16>;
-				};
-				port17: port at 17 {
-					reg = <17>;
-				};
-				port18: port at 18 {
-					reg = <18>;
-				};
-				port19: port at 19 {
-					reg = <19>;
-				};
-				port20: port at 20 {
-					reg = <20>;
-				};
-				port21: port at 21 {
-					reg = <21>;
-				};
-				port22: port at 22 {
-					reg = <22>;
-				};
-				port23: port at 23 {
-					reg = <23>;
-				};
 			};
 		};
 
@@ -219,42 +146,23 @@
 			compatible = "mscc,luton-miim";
 			reg = <0x700a0 0x24>;
 			status = "disabled";
+		};
 
-			phy0: ethernet-phy at 0 {
-				reg = <0>;
-			};
-			phy1: ethernet-phy at 1 {
-				reg = <1>;
-			};
-			phy2: ethernet-phy at 2 {
-				reg = <2>;
-			};
-			phy3: ethernet-phy at 3 {
-				reg = <3>;
-			};
-			phy4: ethernet-phy at 4 {
-				reg = <4>;
-			};
-			phy5: ethernet-phy at 5 {
-				reg = <5>;
-			};
-			phy6: ethernet-phy at 6 {
-				reg = <6>;
-			};
-			phy7: ethernet-phy at 7 {
-				reg = <7>;
-			};
-			phy8: ethernet-phy at 8 {
-				reg = <8>;
-			};
-			phy9: ethernet-phy at 9 {
-				reg = <9>;
-			};
-			phy10: ethernet-phy at 10 {
-				reg = <10>;
-			};
-			phy11: ethernet-phy at 11 {
-				reg = <11>;
+		mdio1: mdio at 700c4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "mscc,luton-miim";
+			reg = <0x700c4 0x24>;
+			status = "disabled";
+		};
+
+		hsio: syscon at 10d0000 {
+			compatible = "mscc,luton-hsio", "syscon", "simple-mfd";
+			reg = <0xa0000 0x10000>;
+
+			serdes_hsio: serdes_hsio {
+				compatible = "mscc,vsc7527-serdes";
+				#phy-cells = <3>;
 			};
 		};
 	};
diff --git a/include/dt-bindings/mscc/luton_data.h b/include/dt-bindings/mscc/luton_data.h
new file mode 100644
index 0000000..e488567
--- /dev/null
+++ b/include/dt-bindings/mscc/luton_data.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#ifndef _LUTON_DATA_H_
+#define _LUTON_DATA_H_
+
+#define SERDES6G(x)     (x)
+#define SERDES6G_MAX    SERDES6G(5)
+#define SERDES_MAX      (SERDES6G_MAX)
+
+/* similar with phy_interface_t */
+#define PHY_MODE_SGMII  2
+#define PHY_MODE_QSGMII 4
+
+#endif
-- 
2.7.4



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