[U-Boot] [PATCH v3 09/18] x86: Update device tree for TPL
Simon Glass
sjg at chromium.org
Thu May 2 16:52:19 UTC 2019
Add TPL binaries to the device x86 binman desciption. When enabled, TPL
will start first, doing the 16-bit init, then jump to SPL and finally
U-Boot proper.
Signed-off-by: Simon Glass <sjg at chromium.org>
---
Changes in v3: None
Changes in v2:
- Add a comment about the hard-coded text base
arch/x86/dts/u-boot.dtsi | 34 ++++++++++++++++++++++++++++++++--
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 1050236330a..9cf733806a5 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -22,7 +22,21 @@
filename = CONFIG_INTEL_ME_FILE;
};
#endif
-#ifdef CONFIG_SPL
+#ifdef CONFIG_TPL
+ u-boot-tpl-with-ucode-ptr {
+ offset = <CONFIG_TPL_TEXT_BASE>;
+ };
+ u-boot-tpl-dtb {
+ };
+ u-boot-spl {
+ offset = <CONFIG_SPL_TEXT_BASE>;
+ };
+ u-boot-spl-dtb {
+ };
+ u-boot {
+ offset = <CONFIG_SYS_TEXT_BASE>;
+ };
+#elif defined(CONFIG_SPL)
u-boot-spl-with-ucode-ptr {
offset = <CONFIG_SPL_TEXT_BASE>;
};
@@ -31,7 +45,19 @@
type = "u-boot-dtb-with-ucode";
};
u-boot {
+ /*
+ * TODO(sjg at chromium.org):
+ * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
+ * for boards with textbase in SDRAM we cannot do this. Just use
+ * an assumed-valid value (1MB before the end of flash) here so
+ * that we can actually build an image for coreboot, etc.
+ * We need a better solution, perhaps a separate Kconfig.
+ */
+#if CONFIG_SYS_TEXT_BASE == 0x1110000
offset = <0xfff00000>;
+#else
+ offset = <CONFIG_SYS_TEXT_BASE>;
+#endif
};
#else
u-boot-with-ucode-ptr {
@@ -77,7 +103,11 @@
offset = <CONFIG_X86_REFCODE_ADDR>;
};
#endif
-#ifdef CONFIG_SPL
+#ifdef CONFIG_TPL
+ x86-start16-tpl {
+ offset = <CONFIG_SYS_X86_START16>;
+ };
+#elif defined(CONFIG_SPL)
x86-start16-spl {
offset = <CONFIG_SYS_X86_START16>;
};
--
2.21.0.1020.gf2820cf01a-goog
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