[U-Boot] [PATCH v1 3/4] armv8: layerscape: enable DMA mode of SD in SPL boot

[Yinbo Zhu]

From: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>

Mark BSS and Heap area of OCRAM as non-secure to perform
DMA from non-secure SD controller.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu at nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/spl.c           |  8 ++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h | 15 ++++++++++++++-
 scripts/config_whitelist.txt                      |  1 +
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 3e53084b21..a6e0af05bf 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
  */
 
 #include <common.h>
@@ -74,6 +75,13 @@ void board_init_f(ulong dummy)
 #endif
 #ifdef CONFIG_VID
 	init_func_vid();
+#endif
+#ifdef CONFIG_TZPC_OCRAM_BSS_HEAP_NS
+	/*
+	 * Mark BSS and HEAP area of OCRAM non-secure
+	 * to support DMA mode in SD.
+	 */
+	out_le32(TZPCR0SIZE_BASE, OCRAM_NONSECURE_SIZE);
 #endif
 	dram_init();
 #ifdef CONFIG_SPL_FSL_LS_PPA
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index eb21c09e01..e7ec71a3da 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2016-2018 NXP
  * Copyright 2015, Freescale Semiconductor
+ * Copyright 2017-2018 NXP
  */
 
 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
@@ -32,6 +32,19 @@
 #define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
 #define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
 
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE			0x02200000
+#define TZPCR0SIZE_BASE			(TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE		(TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE		(TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE		(TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE		(TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE		(TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE		(TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE		(TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE		(TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE		(TZPC_BASE + 0x820)
+
 /* DDR */
 #define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 8c7c1592a5..61de7e0ca0 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4437,6 +4437,7 @@ CONFIG_TWL6030_POWER
 CONFIG_TWR
 CONFIG_TWR_P1025
 CONFIG_TX_DESCR_NUM
+CONFIG_TZPC_OCRAM_BSS_HEAP_NS
 CONFIG_TZSW_RESERVED_DRAM_SIZE
 CONFIG_T_SH7706LSR
 CONFIG_UART_BR_PRELIM
-- 
2.17.1