[U-Boot] [PATCH v2 1/2] arch: armv8: Provide a way to disable cache maintenance ops

[Tom Rini]

On Mon, Apr 22, 2019 at 09:43:32PM +0530, Vignesh Raghavendra wrote:

> On AM654 SoC(arm64) which is IO coherent and has L3 Cache, cache
> maintenance operations being done to support non-coherent platforms
> causes issues.
> 
> For example, here is how U-Boot prepares/handles a buffer to receive
> data from a device (DMA Write). This may vary slightly depending on the
> driver framework:
> 
> 	Start DMA to write to destination buffer
> 	Wait for DMA to be done (dma_receive()/dma_memcpy())
> 	Invalidate destination buffer (invalidate_dcache_range())
> 	Read from destination buffer
> 
> The invalidate after the DMA is needed in order to read latest data from
> memory that’s updated by DMA write. Also, in case random prefetch has
> pulled in buffer data during the “wait for DMA” before the DMA has
> written to it. This works well for non-coherent architectures.
> 
> In case of coherent architecture with L3 cache, DMA write would directly
> update L3 cache contents (assuming cacheline is present in L3) without
> updating the DDR memory. So invalidate after “wait for DMA” in above
> sequence would discard latest data and read will cause stale data to be
> fetched from DDR. Therefore invalidate after “wait for DMA” is not
> always correct on coherent architecture.
> 
> Therefore, provide a Kconfig option to disable cache maintenance ops on
> coherent architectures. This has added benefit of improving the
> performance of DMA transfers as we no longer need to invalidate/flush
> individual cache lines(especially for buffer thats several KBs in size).
> 
> In order to facilitate use of same Kconfig across different
> architecture, I have added the symbol to top level arch/Kconfig file.
> Patch currently disables cache maintenance ops for arm64 only.
> flush_dcache_all() and invalidate_dcache_all() are exclusively used
> during enabling/disabling dcache and hence are not disabled.
> 
> Signed-off-by: Vignesh Raghavendra <vigneshr at ti.com>

Applied to u-boot/master, thanks!

-- 
Tom
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