[U-Boot] [PATCH 2/2] ARM: socfpga: Clear PL310 early in SPL

[Marek Vasut]

On 5/7/19 9:42 PM, Simon Goldschmidt wrote:
> 
> 
> On 07.05.19 21:20, Marek Vasut wrote:
>> On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux
>> will result in stale data in PL310 L2 cache controller. Even if the L2
>> cache controller is disabled via the CTRL register CTRL_EN bit, those
>> data can interfere with operation of devices using DMA, like e.g. the
>> DWMMC controller. This can in turn cause e.g. SPL to fail reading data
>> from SD/MMC.
> 
> I bet this is copy & paste from the gen5 patch? It should probably say
> "On SoCFPGA A10 systems"?

Nice find, fixed.

> Other than that:
> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
Thanks

-- 
Best regards,
Marek Vasut