[U-Boot] Please pull u-boot-x86

Bin Meng bmeng.cn at gmail.com
Wed May 8 11:21:01 UTC 2019


Hi Tom,

This includes the following changes to U-Boot x86 support:

- Allow x86 boards to use TPL, SPL and U-Boot proper
- Update sysreset x86 driver to utilize ACPI registers to do power off
- Add a new chromebook_samus_tpl board for TPL support
- Several minor changes in binman tool

The following changes since commit 8d7f06bbbef16f172cd5e9c4923cdcebe16b8980:

  Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-05-07
09:38:00 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-x86.git

for you to fetch changes up to ffe403762be48d475de4b2b6df87c32fd3a1e8dd:

  x86: samus: Add a target to boot through TPL (2019-05-08 13:02:19 +0800)

----------------------------------------------------------------
Simon Glass (49):
      binman: Don't generate an error in 'text' entry constructor
      binman: Don't show image-skip message by default
      binman: Add a missing comment in Entry_vblock
      binman: Allow sections to have an offset
      dm: core: Fix translate condition in ofnode_get_addr_size()
      spl: Allow sandbox to build a device-tree file
      cros_ec: Use a hyphen in the uclass name
      Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"
      x86: start64: Fix copyright message
      x86: Update a stale comment about ifdtool
      x86: mp_init: Use proper error numbers
      x86: Add a way to reinit the cpu
      x86: dts: Add device-tree labels for rtc and reset
      x86: Support SPL and TPL
      x86: Support booting with TPL
      x86: Add a handoff header file
      x86: broadwell: Improve SDRAM debugging output
      x86: broadwell: Allow SDRAM init from SPL
      x86: broadwell: Move init of debug UART to cpu.c
      x86: broadwell: Split CPU init
      x86: Add support for starting from SPL/TPL
      x86: Allow 16-bit init to be in TPL
      x86: broadwell: Allow booting from SPL
      x86: broadwell: Select refcode and CPU code for SPL
      x86: Add common Intel code for SPL
      x86: Support saving MRC data from SPL
      x86: mrccache: Add more debugging
      x86: pch: Add an ioctl to read power-management info
      x86: ivybridge: Implement PCH_REQ_PMBASE_INFO
      x86: broadwell: Implement PCH_REQ_PMBASE_INFO
      x86: sysreset: Separate out the EFI code
      x86: sysreset: Implement power-off if available
      x86: sysreset: Implement the get_last() method
      x86: Support TPL in Intel common code
      x86: Don't set up MTRRs in SPL
      x86: Don't generate a bootstage report in SPL
      x86: Support PCI VGA ROM when TPL is used
      x86: Add documentation on the samus flashmap
      x86: Update device tree for TPL
      x86: Update device tree for Chromium OS verified boot
      x86: Fix device-tree indentation
      x86: Enable the RTC on all boards
      x86: broadwell: Update PCH to work in TPL
      x86: samus: Increase the pre-reloc memory again
      x86: Add a way to jump from TPL to SPL
      x86: Add a simple TPL implementation
      x86: samus: Update device tree for SPL
      x86: samus: Update device tree for verified boot
      x86: samus: Add a target to boot through TPL

 Makefile                                  |   1 +
 arch/Kconfig                              |  32 ++++++
 arch/x86/Kconfig                          |  10 +-
 arch/x86/Makefile                         |  16 ++-
 arch/x86/cpu/Makefile                     |  15 ++-
 arch/x86/cpu/broadwell/Makefile           |  23 +++-
 arch/x86/cpu/broadwell/cpu.c              | 676
++-----------------------------------------------------------------------------------------------------------------
 arch/x86/cpu/broadwell/cpu_from_spl.c     |  63 +++++++++++
 arch/x86/cpu/broadwell/cpu_full.c         | 694
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/x86/cpu/broadwell/northbridge.c      | 100 ++++++++++++++++++
 arch/x86/cpu/broadwell/pch.c              |  37 ++++++-
 arch/x86/cpu/broadwell/sdram.c            | 136 ++++--------------------
 arch/x86/cpu/i386/cpu.c                   | 113 ++++++++++++--------
 arch/x86/cpu/intel_common/Makefile        |  17 ++-
 arch/x86/cpu/intel_common/car.S           |   2 +-
 arch/x86/cpu/intel_common/cpu_from_spl.c  |  27 +++++
 arch/x86/cpu/ivybridge/bd82x6x.c          |  15 +++
 arch/x86/cpu/mp_init.c                    |  10 +-
 arch/x86/cpu/start.S                      |  13 +++
 arch/x86/cpu/start64.S                    |   2 +-
 arch/x86/cpu/start_from_spl.S             |  71 +++++++++++++
 arch/x86/cpu/start_from_tpl.S             |  49 +++++++++
 arch/x86/cpu/u-boot-spl.lds               |   2 +-
 arch/x86/cpu/x86_64/cpu.c                 |   5 +
 arch/x86/dts/chromebook_samus.dts         |  53 +++++++++-
 arch/x86/dts/reset.dtsi                   |   2 +-
 arch/x86/dts/rtc.dtsi                     |   2 +-
 arch/x86/dts/u-boot.dtsi                  | 162 +++++++++++++++++-----------
 arch/x86/include/asm/handoff.h            |  15 +++
 arch/x86/include/asm/mrccache.h           |  11 ++
 arch/x86/include/asm/spl.h                |  17 ++-
 arch/x86/include/asm/u-boot-x86.h         |  20 ++++
 arch/x86/lib/Makefile                     |   9 +-
 arch/x86/lib/bootm.c                      |   2 +-
 arch/x86/lib/fsp/fsp_car.S                |   2 +-
 arch/x86/lib/init_helpers.c               |   5 +-
 arch/x86/lib/mrccache.c                   |  52 ++++++---
 arch/x86/lib/spl.c                        |  44 +++++++-
 arch/x86/lib/tpl.c                        | 118 +++++++++++++++++++++
 board/google/Kconfig                      |   8 ++
 board/google/chromebook_samus/Kconfig     |  14 ++-
 board/google/chromebook_samus/MAINTAINERS |   7 ++
 configs/chromebook_samus_defconfig        |   2 +-
 configs/chromebook_samus_tpl_defconfig    |  82 ++++++++++++++
 doc/README.x86                            |  16 +++
 drivers/core/ofnode.c                     |   2 +-
 drivers/misc/cros_ec.c                    |   2 +-
 drivers/pci/pci_rom.c                     |   2 +-
 drivers/sysreset/sysreset_x86.c           | 101 ++++++++++++++++--
 include/configs/chromebook_link.h         |   3 -
 include/configs/chromebook_samus.h        |   2 +
 include/configs/qemu-x86.h                |   5 -
 include/configs/x86-common.h              |   1 -
 include/pch.h                             |  18 ++++
 include/pci.h                             |   6 +-
 scripts/Makefile.spl                      |  24 ++++-
 tools/binman/README                       |   7 ++
 tools/binman/bsection.py                  |   9 +-
 tools/binman/control.py                   |   4 +-
 tools/binman/etype/section.py             |   3 +-
 tools/binman/etype/text.py                |   4 +-
 tools/binman/etype/vblock.py              |   1 +
 tools/binman/ftest.py                     |  44 ++++++--
 tools/binman/test/101_sections_offset.dts |  35 ++++++
 64 files changed, 2063 insertions(+), 982 deletions(-)
 create mode 100644 arch/x86/cpu/broadwell/cpu_from_spl.c
 create mode 100644 arch/x86/cpu/broadwell/cpu_full.c
 create mode 100644 arch/x86/cpu/intel_common/cpu_from_spl.c
 create mode 100644 arch/x86/cpu/start_from_spl.S
 create mode 100644 arch/x86/cpu/start_from_tpl.S
 create mode 100644 arch/x86/include/asm/handoff.h
 create mode 100644 arch/x86/lib/tpl.c
 create mode 100644 configs/chromebook_samus_tpl_defconfig
 create mode 100644 tools/binman/test/101_sections_offset.dts

Regards,
Bin


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